I82371MX Datasheet, PDF (61/133 Pages) Intel Corporation – INTEL 430MX PCISET 82371MX MOBILE PCI I/O IDE XCELERATOR (MPIIX)

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82371MX (MPIIX)
3.2.68. SHDW—Shadow Register Access Port
Register Location:
Default Value:
Attribute:
E0h
undefined
Read/Write.
MPIIX includes a set of shadow registers for the standard AT write-only registers. In the transition to Suspend
mode, the content of these registers is saved so the system state can be restored, when resumed. The
shadowed registers can be read through the PCI configuration register.
When written, the SHDW register initializes a counter that points to a shadow register. When the SHDW
Register is read, it returns the data from the shadow register pointed to by the counter. The counter increments
the count every time software reads the register. Tables 3.3−3.5 define the MPIIX shadow registers with the
register counter.
Register
Counter
AT I/O
address
Table 3. DMA 1 Registers
Description
Master DMA
00
00
Channel 0 Base Address Register (low byte).
01
00
Channel 0 Base Address Register (high byte).
02
01
Channel 0 Base Word Count Register (low byte).
03
01
Channel 0 Base Word Count Register (high byte).
04
02
Channel 1 Base Address Register (low byte).
05
02
Channel 1 Base Address Register (high byte).
06
03
Channel 1 Base Word Count Register (low byte).
07
03
Channel 1 Base Word Count Register (high byte).
08
04
Channel 2 Base Address Register (low byte).
09
04
Channel 2 Base Address Register (high byte).
0A
05
Channel 2 Base Word Count Register (low byte).
0B
05
Channel 2 Base Word Count Register (high byte).
0C
06
Channel 3 Base Address Register (low byte).
0D
06
Channel 3 Base Address Register (high byte).
0E
07
Channel 3 Base Word Count Register (low byte).
0F
07
Channel 3 Base Word Count Register (high byte).
10
08
DMA1 Command Register.
11
0B
Channel 0 Mode Register.
12
0B
Channel 1 Mode Register.
13
0B
Channel 2 Mode Register.
14
0B
Channel 3 Mode Register.
15
0F
DMA1 Mask Register.
PRELIMINARY
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