I82371MX Datasheet, PDF (46/133 Pages) Intel Corporation – INTEL 430MX PCISET 82371MX MOBILE PCI I/O IDE XCELERATOR (MPIIX)

82371MX (MPIIX)
E
Bit
7:6
5
4
3
2
1
0
Description
Reserved.
LSTBY_SMI_EN_IDE.
LSTBY_SMI_EN_AUD.
LSTBY_SMI_EN_COM. The address range is defined by the LTMDEV3 Register.
LSTBY_SMI_EN_DEV3. The address range is defined by the LTADEV3 and LTMDEV3
Registers.
LSTBY_SMI_EN_DEV2. The address range is defined by the PAC1 and PAMA Registers.
LSTBY_SMI_EN_DEV1. The address range is by PCSC and PAMA Registers.
3.2.36. LSBTRE—Local Standby Timer Reload Enable Register
Address Offset:
Default Value:
Attribute:
B1h
00h
Read/Write
This register enables/disables local standby timer reloading. When an access is made to one of the enabled
address ranges selected by bits [7:2] (i.e., IDE, Audio, COM port, and Device [3:1]), all six local standby timers
are reloaded with their initial count value. This register also enables/disables motherboard DMA activity on
MDAK[2,1] to reload the Audio Local Standby Timer.
Bit
Description
7
LSTBY_RLD_IDE Enable. 1=Enable. 0=Disable.
6
LSTBY_RLD_AUD Enable. 1=Enable. 0=Disable.
5
LSTBY_RLD_COM Enable. 1=Enable. 0=Disable.
4
LSTBY_RLD_DEV3 Enable. 1=Enable. 0=Disable.
3
LSTBY_RLD_DEV2 Enable. 1=Enable. 0=Disable.
2
LSTBY_RLD_DEV1 Enable. 1=Enable. 0=Disable.
1
AUD MDAK2 Enable. 1=Enable. 0=Disable.
0
AUD MDAK1 Enable. 1=Enable. 0=Disable.
46
PRELIMINARY