I82371MX Datasheet, PDF (67/133 Pages) Intel Corporation – INTEL 430MX PCISET 82371MX MOBILE PCI I/O IDE XCELERATOR (MPIIX)

E
82371MX (MPIIX)
Bit
Description
1:0
DMA Channel Select. Bits [1:0] select the DMA Channel Mode Register to program with bit 2.
Bits [1:0] Channel
00
0 (4)
01
1 (5)
10
2 (6)
11
3 (7)
3.3.1.5. Mask Register—Write All Mask Bits
Register Location:
Default Value:
Attribute:
Channels 0−3—0Fh
Channels 4−7—0DEh
Bit[3:0]=1, Bit[7:4]=0
Read/Write
A channel's mask bit is automatically set to 1 when the Current Byte/Word Count Register reaches terminal
count (unless the channel is programmed for autoinitialization). Setting bits [3:0] to 1 disables all DMA requests
until a clear mask register instruction enables the requests. Note that, masking DMA channel 4 (DMA controller
2, channel 0), masks DMA channels [3:0].
Bit
Description
7:4
Reserved. Must be 0.
3:0
Channel Mask Bits. 1=Disable the corresponding DREQ(s); 0=Enable the corresponding
DREQ(s). Bits [3:0] are set to 1 upon PCIRST or Master Clear.
Bit
Channel
0
0 (4)
1
1 (5)
2
2 (6)
3
3 (7)
PRELIMINARY
67