I82371MX Datasheet, PDF (51/133 Pages) Intel Corporation – INTEL 430MX PCISET 82371MX MOBILE PCI I/O IDE XCELERATOR (MPIIX)

E
82371MX (MPIIX)
3.2.48. SYSMGNTC—System Management Control Register
Address Offset:
Default Value:
Attribute:
C0h
04h
Read/Write
This register freezes all power management timers, enables/disables all power management functions, and
enables/disables the SMI# signal.
Bit
Description
7:3
Reserved.
2
SM_FREEZE. 1=Freeze all power management timers (timers stop counting but retain the
present count).
1
SM_EN. 0=Disable all power management functions.
0
SMI_GATE. 1=Enable SMI. 0=Disable SMI. When enabled, a system management interrupt
condition asserts the SMI# signal. When disabled, the SMI# signal is masked and negated. This
bit only affects the SMI# signal and does not affect the detection/recording of SMI. Thus, if an
SMI is pending when this bit is set to 1, the SMI# signal is asserted.
3.2.49. SYSSMIE—System SMI Enable Register
Address Offset:
Default Value:
Attribute:
C1h
00h
Read/Write
This register enables the generation of SMI (if enabled via the SYSMGNTC Register) for the associated
hardware events (bits [5:0]), and software events (bit 6).
Bit
Description
7
Reserved.
6
APMC_SMI_EN. 1=Enable (a write to the APMC Register generates an SMI#). 0=Disable
5
SWEXT_SMI_EN_EXTSMI. 1=Enable (The occurrence of an EXTSMI# reloads the Software
/EXTSMI# SMI Delay Timer and an SMI is generated after this timer expires.). 0=Disable
4
SYS_SMI_EN_IRQ12. 1=Enable. 0=Disable.
3
SYS_SMI_EN_IRQ8. 1=Enable. 0=Disable.
2
SYS_SMI_EN_IRQ4. 1=Enable. 0=Disable.
1
SYS_SMI_EN_IRQ3. 1=Enable. 0=Disable.
0
SYS_SMI_EN_IRQ1. 1=Enable. 0=Disable.
PRELIMINARY
51