I82371MX Datasheet, PDF (120/133 Pages) Intel Corporation – INTEL 430MX PCISET 82371MX MOBILE PCI I/O IDE XCELERATOR (MPIIX)

82371MX (MPIIX)
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BATLOW# signal prevents a resume in the event of a low battery. A RSMRST# signal is also provided to
ensure that the system is completely reset if the system state is corrupted when the battery backup power is
lost.
• The SUSTAT# output signal provides an indication to the system components and power supply that they
should enter their corresponding suspend mode.
• AT Write-only registers are Shadowed so that the system state can be completely read and saved.
• If DRAM remains active, the suspend refresh is activated.
Suspend-to-DRAM
This mode eliminates the leakage current found in the system by removing power from all components.
However, there is a longer Resume latency, since it must reset and initialize the system. In this mode, power is
removed from the all system components except the DRAM, Real Time Clock, and the Suspend Refresh logic
portion of the MTSC and the MPIIX. MTSC has a separate VCC input for this logic. The SUSTAT# signal is
asserted to inform the system that it can switch off power supplies.
Suspend-to-Disk
This mode eliminates the power consumption of the DRAM Refresh and has a longer Resume latency than
Suspend-to-DRAM, since it must restore the system state from disk. Suspend-to-Disk is similar to Suspend-to-
DRAM except that the DRAM state must be saved and restored. Only the Resume logic and RTC is active
during this mode.
4.8.4.1. Suspend mode selects
For the correct resume sequence to take place, the power management software enables the appropriate
suspend mode in the SUSRSMC2 Register. These bits are powered by the ”Resume Well”.
4.8.4.2. Suspend SMI# Requests (SRBTN# and BATLOW#)
There are two special purpose hardware SMI# sources (SRBTN# and BATLOW# input signals), that are
generally used to indicate that a suspend is requested. Both of these SMI# sources can be disabled by writing a
0 to the SUSP_SMI_EN bit. When the SUSP_SMI_EN bit is written to a 1, the individual SMI enables determine
if the source is enabled. Both of these sources share the Suspend SMI Delay Timer that provides time for the
system to complete current bus master or docking bridge activity.
SRBTN#. The Suspend/Resume Button input generates an SMI# request to the Suspend SMI Delay Timer, if
the SUSP_SMI_EN_SRBTN bit is set to 1 in the in the MISCSMIE Register. When the request is generated, the
delay timer begins to count down. The SRBTN# and EXTSMI# inputs are monitored during a Suspend and can
be used to bring the system out of suspend. (Note: SMI# is not generated by the SRBTN# or EXTSMI# while in
suspend. It is the responsibility of the power management resume routine to generate a software SMI to
complete the resume.)
BATLOW#. During normal operating mode the Battery Low signal is used to generate a suspend request SMI#.
and when the system is in suspend, this signal is used to prevent the system from resuming. The Battery Low
input signal will generate an SMI# request to the Suspend SMI Delay Timer, if the SUSP_SMI_EN_BATLOW bit
is set to 1 in the MISCSMIE Register. When the BATLOW# signal is asserted, the delay timer begins to count
down. The Suspend SMI Delay Timer will stop counting if BATLOW# negates prior to timer reaching zero. It will
resume counting when BATLOW# reasserts or SRBTN# asserts. MPIIX also provides the option to bypass the
SMI# delay timer for a critically low battery condition. BATLOW# assertion generates an immediate SMI# when
the BATLOW_BYPASS_EN bit is set to 1 in the SUSRSMC1 Register. The BATLOW# input is monitored during
a Suspend and can be used to prevent the system from resuming. When the SUSP_SMI_EN_BATLOW bit is
set to a 1, the Battery Low signal prevents MPIIX from initiating a resume.
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PRELIMINARY