I82371MX Datasheet, PDF (90/133 Pages) Intel Corporation – INTEL 430MX PCISET 82371MX MOBILE PCI I/O IDE XCELERATOR (MPIIX)

82371MX (MPIIX)
E
4.4. DMA Controller
The DMA circuitry incorporates the functionality of two 82C37 DMA controllers with seven independently
programmable channels (Channels 0-3 and Channels 5-7). DMA Channel 4 is used to cascade the two
controllers and will default to cascade mode in the DMA Channel Mode (DCM) Register. The DMA controller for
Channels 0-3 is referred to as "DMA-1" and the controller for Channels 4-7 is referred to as "DMA-2".
Channel 0
Channel 1
Channel 2
Channel 3
DMA-1
Channel 4
Channel 5
Channel 6
Channel 7
DMA-2
Figure 3. Internal DMA Controller
052503
DMA channels [3:0] are hardwired to 8-bit, count-by-bytes transfers, and channels [7:5] are programmable to
either 8-bit, count-by-bytes transfers or 16-bit, count-by-words (address shifted) transfers. The MPIIX provides
the timing control and data size translation necessary for DMA transfers between PCI memory and the Extended
I/O Bus I/O or PCI DMA I/O. ISA Compatible DMA and type F (motherboard devices only) timings are
supported.
The MPIIX provides 24-bit addressing in compliance with the ISA Compatible specification. Each channel
includes a 16-bit ISA Compatible Current Register which holds the 16 least significant bits of the 24-bit address,
and an ISA Compatible Low Page Register which contains the eight most significant bits of address. The DMA
controller also permits auto-initialization following a DMA termination.
The DMA controller is at any time either in master mode or slave mode. In master mode, the DMA controller is
either servicing a DMA slave's request for DMA cycles, or allowing a 16-bit ISA master (through the use of the
PCI DMA Serial Protocol) to use the bus via a cascade mode DMA Channel. NOTE: Masters are not supported
on the MPIIX Extended I/O Bus. In slave mode, the MPIIX monitors the PCI bus, decoding and responding to
I/O read and write commands that address its registers.
During DMA memory read cycles to the PCI bus, the MPIIX returns undefined data to the Extended I/O Bus, if
the PCI cycle is either target aborted or master aborted.
The channels can be programmed for single, block, demand, or cascade transfer modes. Each of the three
active transfer modes (single, block, and demand) can perform three different types of transfers (read, write, or
verify). Note that memory-to-memory transfers are not supported by the MPIIX.
ISA compatible timing is provided for DMA slave devices that reside on the Extended I/O Bus. All PCI DMA
cycles use the 4-byte DMA buffer. The buffer reduces PCI utilization resulting from DMA transfers configured for
PCI DMA cycles.
4.4.1. TYPE F TIMING
The type F DMA cycles are used with motherboard devices only, through the use of the MDRQ[2:0] and
MDAK[2:0]# signals. The type F cycles occur back to back at a minimum repetition rate of 3 SYSCLKs (360ns
min). The type F cycles are always performed using the 4-byte DMA buffer.
90
PRELIMINARY