I82371MX Datasheet, PDF (110/133 Pages) Intel Corporation – INTEL 430MX PCISET 82371MX MOBILE PCI I/O IDE XCELERATOR (MPIIX)

82371MX (MPIIX)
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I/O reads to the APMC Register additionally generate STPCLK#, if enabled in the CLKC Register (See Software
Control of STPCLK# section).
4.8.2. CPU POWER MANAGEMENT (CPU, DRAM, L2 CACHE, DATAPATH)
OS Idle Condition. When the OS enters an idle condition, it is waiting for some user input or hardware event to
continue useful work. Since the OS does not require the CPU to execute software, the CPU complex including
the DRAM, L2 cache and datapath, does not need to be running.
The system can indicate an idle condition through hardware (idle timers) or software (O/S, APM) and generate
an SMI# to invoke the power management BIOS. Power management BIOS determines what level of clock
control is required and instructs MPIIX to execute that mode.
Lower Frequency Emulation (Clock Throttling). When the power management software determines that the
system does not require full frequency operation but cannot stop the clock for an indefinite amount of time, the
power management can transition between ON and CPU Standby at a predetermined duty cycle. For example,
at a 50% duty cycle the effective frequency is 1/2 of the CPU CLK frequency.
The Intel 430MX PCIset has 3 independent Clock Control mechanisms: Stop Clock (either CPU Stop Grant
State or CPU Stop Clock State), Clock Throttling, and Auto Clock Throttle.
PCI Clock Control. MPIIX uses the CLKRUN# protocol to provide the capability to stop the PCI clock when
there is no PCI bus activity.
MPIIX generates and controls both the CPU Host Clock (HCLKO) and the PCI clock (PCICLKO) to the system
as illustrated in Figure 13.
4.8.2.1. Stop Clock
The processor can be put in a low power state by externally asserting the STPCLK#. STPCLK# is an interrupt to
the CPU; however, there is not an interrupt acknowledge cycle generated. Once the STPCLK# interrupt is
executed, the processor enters the Stop Grant state. In the Stop Grant state the internal clocks are disabled and
instruction execution is stopped. To exit the Stop Grant state the STPCLK# signal is negated. The CPU power
consumption can be further reduced by stopping the host CLK input to the CPU while in the Stop Grant state,
causing the CPU to enter the Stop Clock state. The Stop Clock state requires a warm-up delay when re-starting
the CLK input to the CPU.
MPIIX waits for the PCICLK to stop before stopping the Host Clock (HCLKO from MPIIX). If the PCI Clock
Control is disabled in the Clock Control Register (PCI_CLK_CTRL_EN bit), the Host Clock cannot be stopped.
In this case the system can enter the Stop Grant state and will not enter the Stop Clock State.
• Entering CPU Stop Grant State
− MPIIX asserts STPCLK#.
− CPU accepts STPCLK# interrupt, flushes buffers, sends the Stop Grant bus cycle.
− MTSC host-to-PCI bridge forwards Stop Grant bus cycle to PCI bus and does PCI master abort.
− MTSC completes the Stop Grant bus cycle by returning a RDY# (BRDY#) to the CPU
− CPU gates the internal clocks to the CPU core and enters the Stop Grant state.
• Leaving the CPU Stop Grant State
− MPIIX negates the STPCLK# input.
− CPU returns to the On state and resumes execution.
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PRELIMINARY