I82371MX Datasheet, PDF (70/133 Pages) Intel Corporation – INTEL 430MX PCISET 82371MX MOBILE PCI I/O IDE XCELERATOR (MPIIX)

82371MX (MPIIX)
E
3.3.1.10. DMA Clear Byte Pointer Register
Register Location:
Default Value:
Attribute:
Channels 0−3—00Ch
Channels 4−7—0D8h
All bits undefined
Write Only
Writing to this register executes the Clear Byte Pointer Command. This command is executed prior to
reading/writing a new address or word count to the DMA. The command initializes the byte pointer flip-flop to a
known state so that subsequent accesses to register contents address upper and lower bytes in the correct
sequence. The Clear Byte Pointer Command (or CPURST or the Master Clear Command) clears the internal
latch used to address the upper or lower byte of the 16-bit Address and Word Count Registers.
Bit
Description
7:0
Clear Byte Pointer. No specific pattern. Command enabled with a write to the I/O port address.
3.3.1.11. DMC—DMA Master Clear Register
Register Location:
Default Value:
Attribute:
Channel 0−3—00Dh
Channel 4−7—0DAh
All bits undefined
Write Only
This software instruction has the same effect as the hardware Reset. The Command, Status, Request,
and Internal First/Last Flip-Flop registers are cleared and the Mask Register is set. The DMA controller
enters the idle cycle. There are two independent Master Clear Commands; 0Dh acts on channels 0-3, and
0DAh acts on channels 4-7.
Bit
Description
7:0
Master Clear. No specific pattern. Command enabled with a write to the I/O port address
3.3.1.12. DCLM—DMA Clear Mask Register
Register Location:
Default Value:
Attribute:
Channel 0−3—00Eh
Channel 4−7—0DCh
All bits undefined
Write Only
This command clears the mask bits of all four channels.
Bit
Description
7:0
Clear Mask Register. No specific pattern. Command enabled with a write to the I/O port address.
70
PRELIMINARY