I82371MX Datasheet, PDF (6/133 Pages) Intel Corporation – INTEL 430MX PCISET 82371MX MOBILE PCI I/O IDE XCELERATOR (MPIIX)

82371MX (MPIIX)
E
3.4.2. APMS—ADVANCED POWER MANAGEMENT STATUS PORT ...............................................83
4.0. FUNCTIONAL DESCRIPTION...............................................................................................................84
4.1. Memory And I/O Address Map ...............................................................................................................84
4.1.1. I/O ACCESSES................................................................................................................................84
4.1.2. BIOS MEMORY ACCESS ...............................................................................................................84
4.1.3. PERIPHERAL CHIP SELECTS ......................................................................................................85
4.2. PCI Interface............................................................................................................................................86
4.2.1. TRANSACTION TERMINATION ....................................................................................................86
4.2.2. PARITY SUPPORT .........................................................................................................................86
4.2.3. PCI ARBITRATION .........................................................................................................................87
4.2.4. PCI CLOCK CONTROL (CLKRUN#) .............................................................................................87
4.3. Extended I/O Bus ....................................................................................................................................87
4.3.1. EXTENDED I/O BUS CYCLES FOR MPIIX AS A MASTER (PCI MASTER INITIATED) .........88
4.3.2. EXTENDED I/O BUS DMA (8-BIT AND 16-BIT TRANSFERS) ...................................................89
4.4. DMA Controller........................................................................................................................................90
4.4.1. TYPE F TIMING ...............................................................................................................................90
4.4.2. DMA buffer for PCI DMA type F transfers ......................................................................................91
4.4.3. EXTENDED I/O BUS DMA ARBITRATION ..................................................................................91
4.4.4. PCI DMA...........................................................................................................................................91
4.4.4.1. PCI DMA Expansion Protocol ..................................................................................................91
4.4.4.2. PCI DMA Expansion Cycles ....................................................................................................92
4.4.4.3. Normal DMA Cycle ...................................................................................................................94
4.4.4.4. Normal DMA Cycle with Terminal Count ................................................................................95
4.4.4.5. Verify DMA Cycle ......................................................................................................................96
4.4.4.6. Verify DMA Cycle with Terminal Count ...................................................................................97
4.5. IDE Interface............................................................................................................................................98
4.5.1. ATA REGISTER BLOCK DECODE ...............................................................................................98
4.5.2. ENHANCED TIMING MODES ........................................................................................................99
4.5.2.1. IORDY masking ..................................................................................................................... 100
4.5.2.2. PIO 32 bit IDE data port mode .............................................................................................. 100
4.6. Interval Timer ....................................................................................................................................... 100
4.7. Interrupts............................................................................................................................................... 101
4.7.1. PROGRAMMING THE INTERRUPT CONTROLLER ............................................................... 101
4.7.1.1. Edge and Level Triggered Mode .......................................................................................... 102
4.7.2. INTERRUPT STEERING ............................................................................................................. 102
4.7.3. MOUSE FUNCTION ..................................................................................................................... 103
4.7.4. COPROCESSOR ERROR FUNCTION ...................................................................................... 103
4.7.5. NMI SUPPORT ............................................................................................................................. 103
4.8. Power Management Support .............................................................................................................. 104
4.8.1. SMI GENERATION....................................................................................................................... 106
4.8.1.1. SMI Enables ........................................................................................................................... 106
6
PRELIMINARY