I82371MX Datasheet, PDF (111/133 Pages) Intel Corporation – INTEL 430MX PCISET 82371MX MOBILE PCI I/O IDE XCELERATOR (MPIIX)

E
82371MX (MPIIX)
• Entering CPU Stop Clock State
− MPIIX asserts STPCLK#.
− CPU accepts STPCLK# interrupt, flushes buffers, sends the STOP GRANT bus cycle.
− MTSC host-to-PCI bridge forwards Stop Grant bus cycle to PCI bus and does PCI Master Abort.
− MTSC completes the Stop Grant bus cycle by returning a RDY# (BRDY#) to the CPU
− CPU gates the internal clocks to the CPU core and enters the Stop Grant state.
− MPIIX stops the CLK input to the CPU only AFTER the RDY# has been returned to the CPU.
• Leaving the CPU Stop Clock State
− MPIIX starts the CLK input to the CPU and waits for the CLK Start Latency timer to expire (about 1 ms).
− MPIIX negates STPCLK#.
− CPU returns to the On state and resumes normal execution.
HCLK
SRAM
CPU
PCLK
MTDP
MTSC
MPIIX
PCICLKO
HCLKO
PCICLK
OSC
RTCCLK1
HCLK
LCD PPEC BRIDGE
14.31818 MHz
32 KHz
60 MHz
Figure 13. Intel 430MX PCIset Clock Distribution
PRELIMINARY
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