I82371MX Datasheet, PDF (47/133 Pages) Intel Corporation – INTEL 430MX PCISET 82371MX MOBILE PCI I/O IDE XCELERATOR (MPIIX)

E
82371MX (MPIIX)
3.2.37. LSBSMIS—Local Standby SMI Status Register
Address Offset:
Default Value:
Attribute:
B2h
00h
Read/Write
The bits in this register indicate that the corresponding Local Standby Timer expired and caused an SMI. SMI
generation for the timers are globally enabled via the GSMIE Register and individually enabled via the LSBMIE
Register. MPIIX sets the request bits to a 1. Software clears a bit by writing a 0 to it. If MPIIX is setting the bit to
a 1 at the same time that software is setting it to 0, the bit is set to 1.
Bit
Description
7:6
Reserved.
5
LSTBY_STAT_IDE. 1=IDE Local Standby Timer generated an SMI#.
4
LSTBY_STAT_AUD. 1=Audio Local Standby Timer generated an SMI#.
3
LSTBY_STAT_COM. 1=COM Port Local Standby Timer generated an SMI#.
2
LSTBY_STAT_DEV3. 1=Device 3 Local Standby Timer generated an SMI#.
1
LSTBY_STAT_DEV2. 1=Device 2 Local Standby Timer generated an SMI#.
0
LSTBY_STAT_DEV1. 1=Device 1 Local Standby Timer generated an SMI#.
3.2.38. LSBTIDE—Local Standby IDE Timer Register
Address Offset:
Default Value:
Attribute:
B4h
00h
Read/Write
This register provides the idle time interval for generating an SMI#. An eight second internal clock provides an
idle timeout range of 8 sec. to 34 minutes. The timer can be frozen via the SYSMGNTC Register. The timer is
reloaded with the count value programmed into this register when there is an access to the enabled device
address, the individual enable bit is set in the LSBSMIE Register, or access to a device enabled in the LSBTRE
register.
Bit
Description
7:0
LSTBY_TMR_IDE. This field contains an 8-bit value for the IDE Local Standby Timer. 00h is an
illegal programmed value.
PRELIMINARY
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