I82371MX Datasheet, PDF (11/133 Pages) Intel Corporation – INTEL 430MX PCISET 82371MX MOBILE PCI I/O IDE XCELERATOR (MPIIX)

E
82371MX (MPIIX)
2.0 SIGNAL DESCRIPTION
This section provides a detailed description of each signal. The signals are arranged in functional groups
according to their associated interface.
The '#' symbol at the end of a signal name indicates that the active, or asserted state occurs when the signal is
at a low voltage level. When '#' is not present after the signal name, the signal is asserted when at the high
voltage level.
The terms assertion and negation are used extensively. This is done to avoid confusion when working with a
mixture of 'active-low' and 'active-high' signals. The term assert, or assertion indicates that a signal is active,
independent of whether that level is represented by a high or low voltage. The term negate, or negation
indicates that a signal is inactive.
Certain signals are used to drive other signals with different functions through external buffers or transceivers.
Both functions have been noted in the descriptions below, with the signal whose function is being described in
bold font. The actual name given to the pin is the signal driven by MTSC.
The “PCIRST#” column indicates the state of the signals during reset.
The following notations are used to describe the signal type.
I
O
o/d
t/s
s/t/s
3.3V
5/3V
pu
pd
bk
Input is a standard input-only signal.
Totem pole output is a standard active driver.
Open drain.
Tri-State is a bi-directional, tri-state input/output pin.
Sustained tri-state is an active low tri-state signal owned and driven by one and only one agent at a time.
The agent that drives a s/t/s pin low must drive it high for at least one clock before letting it float. A new
agent can not start driving a s/t/s signal any sooner than one clock after the previous owner tri-states it.
An external pull-up is required to sustain the inactive state until another agent drives it and must be
provided by the central resource.
Indicates a standard 3.3V low voltage TTL interface.
Indicates that this signal is normally 5V, but will be powered by the RTC voltage on the VDDR “resume
well” power supply pin during the suspend state at normal 3.3 volts.
Internal Pull-Up
Internal Pull-Down
Internal Bus Keeper
2.1. PCI Interface Signals
Signal Name Type
PCIRST#
AD[31:0]
I/O
Tri-state
5V
C/BE[3:0]#
I/O
Tri-state
5V
Description
PCI ADDRESS/DATA: The standard PCI address and data
lines. The address is driven with FRAME# assertion and data
is driven or received in following clocks.
BUS COMMAND AND BYTE ENABLES: The command is
driven with FRAME# assertion. Byte enables corresponding
to supplied or requested data is driven on following clocks.
PRELIMINARY
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