I82371MX Datasheet, PDF (89/133 Pages) Intel Corporation – INTEL 430MX PCISET 82371MX MOBILE PCI I/O IDE XCELERATOR (MPIIX)

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82371MX (MPIIX)
MPIIX provides the Fast A20Gate bit 1 in the Port 92h Register and ALTA20M output signal. This signal is
externally OR’d with the A20M from the Keyboard Controller and then sent to the CPU. MPIIX also provides the
Fast CPU INIT bit 0 in the Port 92h Register and the INIT signal (Figure 2). This signal is externally OR’d with
the RC# signal from the Keyboard Controller.
KBA20
Keyboard
Controller
RC#
P92 FAST_A20
MPIIX
P92 FAST_INIT
ALT_A20
INIT
A20M#
INIT
Pentium ^R
Processor
Figure 2. Fast A20Gate and INIT Connections
052502
4.3.2. EXTENDED I/O BUS DMA (8-BIT AND 16-BIT TRANSFERS)
The DMA controller in MPIIX will transfer data between PCI memory and Extended I/O bus. Devices on the
Extended I/O bus request DMA service through the MDRQ[2:0]/MDAK[2:0]# or DREQ2/DACK2# signal pairs.
The MDRQ[2:0]/MDAK[2:0]# signal pairs can be routed to any of the channels on the DMA controller.
For 8-bit DMA transfers, data is read/written on the SD[7:0]. SA[15:0] are driven to 0 which prevents any other
I/O devices on the Extended I/O bus from responding to the DMA cycle. MPIIX does not need an AEN signal for
systems that only implement 8-bit DMA devices on the Extended I/O bus.
For 16-bit DMA transfers the upper byte of data (SD[15:8]) is multiplexed on the SA[15:8] signal pins. For 16-bit
DMA cycles, the MPIIX asserts MDAKx#, IOR# or IOW#, and floats (DMA read) or drives (DMA write) the
SA[15:8] signals. For systems that use 16-bit DMA transfers on the Extended I/O bus, the SA[15:8] signals are
driven with data by either the MPIIX or the 16-bit DMA device. To prevent 8-bit I/O devices from responding to
the address and command from the 16-bit DMA cycle, these 8-bit I/O devices require an AEN signal. The AEN
signal can be generated by inverting the MDAKx# signal that is assigned to the 16-bit DMA device.
NOTE
For 8-bit I/O read cycles to the 16-bit DMA device, it is possible that the 16-bit DMA device could drive
data onto its SD[15:8]. If SA[15:8] are connected directly to the SD[15:8] signals of the 16-bit DMA device,
there will be contention. In this case the SD[15:8] signals to/from the 16-bit DMA device will require
buffering with a ‘245 transceiver. The ‘245 can use MDAKx# for an enable and the MPIIX IOR# signal for
the direction. (Note: this is simply a caution since the ISA specification prohibits driving the upper byte on
a byte-wide access. However, there have been devices that were in violation of this specification)
PRELIMINARY
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