I82371MX Datasheet, PDF (55/133 Pages) Intel Corporation – INTEL 430MX PCISET 82371MX MOBILE PCI I/O IDE XCELERATOR (MPIIX)

E
82371MX (MPIIX)
Bit
3
2
1:0
Description
SUS_REF. This bit is set by the power management software at the end of the suspend
routine. The SUS_STAT bit is set automatically by MPIIX when the SUS_REF bit is set by
software. This bit is shadowed in the MTSC to initiate the suspend refresh.
SUS_STAT. This bit can be set by power management software at the end of the suspend
routine. In addition, this bit is set to 1 by the MPIIX when the SUS_REF bit is set to 1. This bit is
set to 0 by the power managment resume routine.
SUS_MODE. This field sets the suspend mode.
Bits[1:0] Function
00
Suspend is Disabled
01
Reserved (illegal)
10
Suspend-to-DRAM
11
Suspend-to-Disk
3.2.56. SUSRSMC2—Suspend/Resume Control 2 Register
Address Offset:
Default Value:
Attribute:
CDh
00h
Read/Write
This register prevents EXTSMI# from causing a resume event.
Bit
Description
7:1 Reserved.
0
RSM_MSK_EXTSMI. 1=EXTSMI# will not cause a resume event.
3.2.57. SMOUTC—SMOUT Control Register
Address Offset:
Default Value:
Attribute:
CEh
3Fh
Read/Write
This register controls the SMOUT[5:0] signals.
Bit
Description
7:6
Reserved.
5:0
SMOUT[5:0]. Writing to any of these bits causes that logical level to be driven on the
corresponding SMOUTx signal. When the dual function SMOUT5/DOE# signal is configured for
Disk Output Enable (DOE#), writing to the SMOUT5 bit has no effect. When the dual function
SMOUT4/RTCALE signal is configured for RTCALE, writing to the SMOUT4 bit has no effect.
PRELIMINARY
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