I82371MX Datasheet, PDF (39/133 Pages) Intel Corporation – INTEL 430MX PCISET 82371MX MOBILE PCI I/O IDE XCELERATOR (MPIIX)

E
82371MX (MPIIX)
Bit
Description
2:0
DMA Channel. This field indicates what DMA Channel the signal pair controls. This allows the
request/grant pair to be software routable to any DMA channel. Valid values for the DMA Channel
field are:
Bits[3:1] Channel
Bits[3:1] Channel
000
DMA Channel 0
100
Reserved
001
DMA Channel 1
101
DMA Channel 5
010
DMA Channel 2
110
DMA Channel 6
011
DMA Channel 3
111
DMA Channel 7
Note that MPIIX does not support the use of the PC/PCI REQ#/GNT# pair for PCI Masters. Do not
program the channel field to the reserved value of 100.
3.2.21. PMAC[1:0]—PROGRAMMABLE MEMORY ADDRESS CONTROL REGISTERS
Address Offset:
Default Value:
Attribute:
8A–8Bh (PMAC0), 8C–8Dh (PMAC1)
0000h
Read/Write
This register provides the memory addresses to be used as Burst Event, Clock Throttle Break Event, or
Peripheral Access Detect. The memory address is programmable in the range between 16 Kbytes and 1 Gbyte.
The memory range is programmable between 16 Kbytes and 4 Mbytes using the Programmable Memory
Address Mask (PMAM) registers.
Note:
The memory address must be aligned to the size of the memory range programmed through the PMAM
registers. Thus, if the range is 16 Kbytes, the memory address range can start on any 16-Kbyte address
boundary), If the memory range is 4 Mbytes, the memory address range can start on any 4 Mbytes
address boundary.
Bit
Description
15:0 Memory Address Control (MAC). This field is compared against PCI addresses AD[29:14]
during memory cycles. The upper 2 addresses (AD[31:30]) must be zero for the address to be
decoded.
PRELIMINARY
39