I82371MX Datasheet, PDF (50/133 Pages) Intel Corporation – INTEL 430MX PCISET 82371MX MOBILE PCI I/O IDE XCELERATOR (MPIIX)

82371MX (MPIIX)
E
3.2.45. SUSSMIT—Suspend SMI Delay Timer Register
Address Offset:
Default Value:
Attribute:
BDh
00h
Read/Write
This timer generates a delay between the hardware generation of a suspend or resume (asserting the SRBTN#
signal) or a battery low indication (asserting the BATLOW# signal) and the corresponding SMI generation. A 128
msec internal clock provides a time delay range of 128 msec to 32 sec. For the SRBTN# or BATLOW# signals
to activate this delay timer, there individual enable bits must be set to 1 in the MISCSMIE Register. Note that the
generation of BATLOW# can bypass this delay timer and immediately generate an SMI by programming this
feature in the SUSRSMC1 Register.
Bit
Description
7:0
SUSP_SMI_DLY_TMR. This field contains an 8-bit count value for the Suspend/Resume Button
SRBTN# and Battery Low BATLOW# SMI Delay Timer. 00h is an illegal programming count.
3.2.46. GSBTMR—Global Standby Timer Register
Address Offset:
Default Value:
Attribute:
BEh
00h
Read/Write
This register provides a global standby timer interval for generating an SMI#. An eight second internal clock
provides a standby timeout range of 8 sec to 34 minutes. This timer is enabled via the GSMIE Register. The
timer is reloaded when the enable bit is set, the timer expires, any local standby timer is reloaded, or any
enabled system event specfied by the SYSEVNTE[2:0] Registers. A status bit in the GSMIS Register indicates
that this timer generated the SMI.
Bit
Description
7:0
GSTBY_TMR. This field contains an 8-bit count value for the Global Standby Timer. 00h is an
illegal programmed value.
3.2.47. CLKTHSBYT — Clock Throttle Standby Timer Register
Address Offset:
Default Value:
Attribute:
BFh
00h
Read/Write
This register provides the count for STPCLK# negation (no CLKTHL Break Event detected). The MPIIX starts to
throttle the clock when the timer expires. The timer can be programmed via bit 7 in Clock Control Register (offset
D4h) with the granularity of 4 ms or 32 ms. This provides the timer a range of 4 ms to 1 sec, or 32 ms to 8 sec,
respectively. The timer is reloaded everytime an enabled CLKTHL Break Event is detected.
Bit
Description
7:0
CLKTHL_STBY_TMR: This field contains the count value for the STPCLK# deassertion (no
CLKTHL Break Event detected). 00h is an illegal programmed count.
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PRELIMINARY