I82371MX Datasheet, PDF (54/133 Pages) Intel Corporation – INTEL 430MX PCISET 82371MX MOBILE PCI I/O IDE XCELERATOR (MPIIX)

82371MX (MPIIX)
E
Bit
0
Reserved.
Description
3.2.54. GSMIS — Global SMI STATUS Register
Address Offset:
Default Value:
Attribute:
C8h
00h
Read/Write
This register indicates whether a system event, EXTSMI#, or the software SMI (via bit 0 of the GSMIE Register)
generated the SMI. The register also indicates whether a write to the APMC Register, one of the local traps, one
of the local standby timers, the global standby timer, or one of the suspend hardware events caused an SMI.
The MPIIX sets these bits to a 1 and software sets these bits to 0 by writing a 0 to the individual bit(s). If the
MPIIX is setting a bit to 1 at the same time that software is setting it to a 0, the bit is set to 1.
Bit
Description
7
SYS_STAT. 1=One of the system SMI events in the SYSEVNT[2:0] Registers caused the
SMI#.
6
SWEXT_STAT. 1=Software SMI (programming bit 0 of the GSMIE Register) or EXTSMI#
caused the SMI.
5
APM_STAT. 1=Write to APMC Register caused SMI.
4
LTRP_STAT. 1=Access to one of the Local Traps caused an SMI.
3
LSTBY_STAT. 1=One of the Local Standby Timers expired and caused an SMI.
2
GSTBY_STAT. 1=Global Standby Timer expired and caused an SMI.
1
SUSP_STAT. 1=SRBTN# or BATLOW# caused an SMI.
0
Reserved.
3.2.55. SUSRSMC1—Suspend/Resume Control 1 Register
Address Offset:
Default Value:
Attribute:
CCh
70h
Read/Write
The software programmable bits in this register control various suspend/resume functions. This register also
enables the BATLOW# signal to bypass the Suspend SMI Delay Timer and immediately generate an SMI.
Bit
Description
7
BATLOW_BYPASS_EN. When bit 7=1 (and bit 1=1 in the MISCSMIE Register), the
BATLOW# input bypasses the Suspend SMI Delay Timer and cause an SMI# directly. When
this bit is set to 0, the BATLOW# SMI waits for the timer to expire.
6
RSM_MSK_IRQ8. 1=IRQ8# will not cause a resume.
5
RSM_MSK_COMRI. 1=COMRI# will not cause a resume.
4
RSM_MSK_BATLOW. 1=BATLOW# will not PREVENT a resume.
54
PRELIMINARY