I82371MX Datasheet, PDF (33/133 Pages) Intel Corporation – INTEL 430MX PCISET 82371MX MOBILE PCI I/O IDE XCELERATOR (MPIIX)

E
82371MX (MPIIX)
3.2.12. PIRQRC [A,B]—PIRQX ROUTE CONTROL REGISTERS
Address Offset :
Default Value:
Attribute:
60h (PIRQRCA) – 61h (PIRQRCB)
80h
Read/Write
These registers control the routing of PIRQ[A,B] to the IRQ inputs of the interrupt controller. Each PIRQx# can
be independently routed to any one of 11 interrupts. Both PIRQx# lines can be routed to the same IRQx input.
Note, that the IRQ selected through bits [3:0] must be set to level sensitive mode in the corresponding ELCR
Register. When a PIRQ# line is routed to a given IRQ input to the internal 8259, the corresponding IRQ is
masked
Bit
Description
7
Interrupt Routing Enable. 0=enable. 1=disable.
6:4
Reserved. Read as 0s.
3:0
Interrupt Routing: When bit 7=0, this field selects the routing of the PIRQx to one of the interrupt
controller interrupt inputs.
Bits [3:0]
IRQ Routing
Bits [3:0]
IRQ Routing
0000
0001
0010
0011
0100
0101
0110
0111
Reserved
Reserved
Reserved
IRQ3
IRQ4
IRQ5
IRQ6
IRQ7
1000
1001
1010
1011
1100
1101
1110
1111
Reserved
IRQ9
IRQ10
IRQ11
IRQ12
Reserved
IRQ14
IRQ15
3.2.13. MSTAT—MISCELLANEOUS STATUS REGISTER
Address Offset:
Default Value:
Attribute:
6Bh–6Ah
xxxx xxxx xxxx x00S (S=Strapping option)
Read Only
This register reports the hardware strapping options selected for the Extended I/O Bus clock divisor.
Bit
Description
15:3
Reserved. Software should not rely on any particular value in this field.
2:1
Reserved. Read as 0.
0
ISA Clock Divisor Status: This bit reports the strapping option on the SYSCLK signal. 1=clock
divisor of 3 (PCICLK=25 MHz). 0 (default)=Clock divisor of 4 (PCICLK=33 MHz). Note that, for
PCICLK=30 MHz, a clock divisor of 4 must be selected and produces a SYSCLK of 7.5 MHz.
PRELIMINARY
33