I82371MX Datasheet, PDF (34/133 Pages) Intel Corporation – INTEL 430MX PCISET 82371MX MOBILE PCI I/O IDE XCELERATOR (MPIIX)

82371MX (MPIIX)
E
3.2.14. IDETIM—IDE TIMING REGISTER
Address Offset:
Default Value:
Attribute:
6D–6Ch: Primary/Secondary Channel
0000h
Read/Write
This register controls the MPIIX's IDE interface and selects the timing characteristics of the PCI Local Bus IDE
cycle.
Bit
Description
15
IDE Decode Enable (IDE): When bit 15=1 (Enable), PCI I/O accesses to the IDE ATA
register blocks (command block and control block) are forwarded to the IDE interface. When
bit 15=0, MPIIX does not claim the PCI cycle.
14
Primary or Secondary IDE Address Decode. 0=Primary. 1=Secondary. Bit 15 must be 1 to
decode IDE cycles on PCI.
13:12
IORDY Sample Point (ISP). This field determines the number of clocks between DIOx#
assertion and the first IORDY# sample point.
Bits [13:12]
Number of Clocks
00
5
01
4
10
3
11
2
11:10
Reserved.
9:8
Recovery Time (RCT). This field determines the minimum number of clocks between the
last IORDY# sample point and the DIOx# strobe of the next cycle.
Bits [9:8]
Number of Clocks
00
4
01
3
10
2
11
1
7
Reserved.
6
Prefetch and Posting Enable (PPE1). When this bit is set, prefetch and posting to the IDE
data port is enabled for drive 1.
5
IORDY Sample Point Enable Drive Select 1 (IE1). When IE1=0, IORDY sampling is
disabled for Drive 1. The internal IORDY signal is forced asserted guaranteeing that IORDY
is sampled asserted at the first sample point as specified by the ISP field in this register.
When IE1=1 and the currently selected drive (via a copy of bit 4 of 1x6h) is Drive 1, all
accesses to the enabled I/O address range sample IORDY. The IORDY sample point is
specified by the ISP field in this register.
34
PRELIMINARY