I82371MX Datasheet, PDF (122/133 Pages) Intel Corporation – INTEL 430MX PCISET 82371MX MOBILE PCI I/O IDE XCELERATOR (MPIIX)

82371MX (MPIIX)
E
The COMRI# input has an internal 50 KΩ pull-up resistor that maintains a valid logic level on this input when it is
not connected to any device. If the COMRI# input is left un-connected, the COMRI# input should NOT be
masked as a resume event. When the COMRI# input is masked as a resume event, the COMRI# input pull-up
resistor is disabled while in suspend mode. If the device that generates COMRI# is powered during suspend and
the COMRI# input is masked as a resume event, the internal pull-up is disabled and there will not be a DC path.
If the device that generates COMRI# is powered down during suspend, the COMRI# input should be masked as
a resume event. This disables the MPIIX internal pull-up resistor and prevents a DC path between VCC and the
COMRI# device’s power plane (the COMRI# signal to float to ground in this case). The COMRI# input is masked
as a resume event in the default state after PCIRST#.
The EXTSMI# signal has an internal 8 KΩ pull-up resistor. When EXTSMI# is masked as a resume event, the
pull-up resistor is disabled while the system is in suspend mode. If the EXTSMI# input is left un-connected, the
EXTSMI# input must NOT be masked as a resume event. This prevents the EXTSMI# input from floating since
the internal pull-up resistor is enabled. After PCIRST# the EXTSMI# input defaults to NOT masked as a resume
event.
Power management software can pole the real-time clock, COMRI# device, and EXTSMI# devices to determine
the source of the resume event. If none of these devices caused the resume event, the SRBTN# was the default
cause of the resume.
If the RTC alarm (attached to IRQ8#) is the resume event, it must be cleared by the resume SMI handler. The
8259-compatible programmable interrupt controller is not powered during suspend and an interrupt will not be
generated. A read to the RTC Status Register (I/O address 0Ch) clears the alarm status bit and causes IRQ8#
to be negated.
Battery Low indication (BATLOW# signal) can be masked such that it will not prevent a resume when both
BATLOW# and a resume event are active. The MPIIX privides a Resume RESET input (RSMRST# signal) to
reset the entire system (including Resume logic and the RTC content) when the RTC power can not sustain a
“valid” suspend mode.
4.8.4.4. POWER PLANE CONTROL
The SUSTAT# signal indicates that the system logic has entered a suspend mode and that the appropriate
power planes can be turned off. For suspend-to-DRAM, the MPIIX (and MTSC component) requires power to
the “Resume Well”. DRAM (and Video RAM) also requires power during this suspend state. Additional logic is
required to gate the SUSTAT# signal to the power planes that supply the power to the “Resume Well” and
DRAM. This gate should be controlable by power management software through the keyboard controller or other
programmable logic.
Timing Requirements
• PWROK. All power supplies must be stable for at least 1ms before PWROK is asserted to the
MPIIX/MTSC.
• PWRSD. The VDDM DRAM and VDDR MTSC Resume Well power supplies must be stable for at least 1
ms before PWRSD is asserted to the MTSC.
• CPU and PCI Reset. The Power Supply and Clocks (HCLK, PCICLK) must be stable for 1ms before CPU
and PCI Resets are de-asserted. MPIIX drives the PCIRST# signal for at least 1 ms after the PWROK signal
is asserted. MPIIX drives the CPURST signal for at least 2 ms after the PWROK signal is asserted.
Notes:
1. The SUSTAT# signal from the MPIIX is used to switch off the power supplies when entering suspend mode.
Systems that require both Suspend-to-DRAM and Suspend-to-DISK must distinguish between the two
different suspend modes to turn off the appropriate power supplies when SUSTAT# asserted.
122
PRELIMINARY