I82371MX Datasheet, PDF (84/133 Pages) Intel Corporation – INTEL 430MX PCISET 82371MX MOBILE PCI I/O IDE XCELERATOR (MPIIX)

82371MX (MPIIX)
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4.0. FUNCTIONAL DESCRIPTION
This section describes each of the major functions of the MPIIX including the memory and I/O address map, PCI
interface, Extended I/O Bus interface, DMA controller, IDE interface, interval timer, interrupts, power
management, and reset.
4.1. Memory And I/O Address Map
The MPIIX interfaces to two system busesPCI Bus and the Extended I/O Bus. The MPIIX provides positive
decode for certain I/O and memory space accesses on the PCI bus as described in this section. The MPIIX
does not support other bus masters on the Extended I/O Bus and, thus, does not provide address decoding on
this bus.
4.1.1. I/O ACCESSES
The MPIIX provides positive decode for PCI accesses to the PCI Configuration Registers, power management
registers, and the ISA-Compatible registers. For details concerning accessing these registers, see the Register
Description section.
PCI I/O access that are claimed by MPIIX, and are not part of the MPIIX internal register set, are forwarded to
the Extended I/O Bus. These accesses are targeted for peripherals residing on the Extended I/O Bus.
4.1.2. BIOS MEMORY ACCESS
The MPIIX supports 256 Kbytes of BIOS space. This includes the normal 128 Kbyte space plus an additional
128 Kbyte BIOS space (known as the extended BIOS area). The BIOSE Register provides BIOS space access
control. Access to the lower 64 Kbyte block of the 128 Kbyte space and the extended BIOS space can be
individually enabled/disabled. In addition, write protection can be programmed for the entire BIOS space.
The MPIIX only claims PCI memory cycles in the BIOS range, and forwards the cycles to the Extended I/O Bus.
The 128 Kbyte BIOS memory space is located at 000E0000−000FFFFFh (top of 1 Mbyte), and is aliased at
FFFE0000h (top of 4 GBytes). This 128 Kbyte block is split into two 64 Kbyte blocks. Accesses to the top 64
Kbytes (000F0000–000FFFFFh) will be forwarded to the Extended I/O bus and BIOSCS# is always generated.
Accesses to the bottom 64 Kbytes (000E0000–000EFFFFh) are forwarded to the Extended I/O bus and
BIOSCS# generated based on the status of bits [6:4] in the BIOSE Register. Accesses to the aliased region at
the top of 4 GBytes (FFFF0000h–FFFFFFFFh) will be forwarded to the Extended I/O bus and BIOSCS# will
always be generated. Accesses to the aliased region at the top of 4 GBytes (FFFE0000–FFFEFFFFh) are
forwarded to the Extended I/O bus and BIOSCS# generated based on the status of bits [6:4] in the BIOSE
Register.
The additional 128 Kbyte region resides at FFFC0000–FFFDFFFFh. Memory accesses within this region are
forwarded to the Extended I/O bus and BIOSCS# is generated if bit 7 in the BIOSE Register is enabled.
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PRELIMINARY