I82371MX Datasheet, PDF (52/133 Pages) Intel Corporation – INTEL 430MX PCISET 82371MX MOBILE PCI I/O IDE XCELERATOR (MPIIX)

82371MX (MPIIX)
E
3.2.50. MISCSMIE—Misc SMI Enable Register
Address Offset:
Default Value:
Attribute:
C2h
00h
Read/Write
This register enables a PCI interrupt for a write to the APCM Register, and enables the SRBTN# and BATLOW#
signals to generate an SMI.
Bit
Description
7:4
Reserved.
3
APM_CALLBACK_EN. When bit 3=1 (and the APMC SMI is enabled in the SYSSMIE
Register), a write to the APMC Register generates a PCI interrupt (PIRQA). PIRQA can be
steered to any available interrupt on the interrupt controller.
2
SUSP_SMI_EN_SRBTN. 1=Enable (SRBTN# assertion causes an SMI, if enabled in the
GSMIE Register). 0=Disable.
1
SUSP_SMI_EN_BATLOW. 1=Enable (BATLOW# assertion causes an SMI, if enabled in the
GSMIE Register). 0=Disable.
0
Reserved.
3.2.51. GSMIE—Global SMI Enable Register
Address Offset:
Default Value:
Attribute:
C3h
00h
Read/Write
This register provides a master SMI enable for the system events, software SMI# and EXTSMI#, local traps,
local standby timers, the global standby timer, and SRBTN# and BATLOW# suspend signals. The register also
enables the Software/EXTSMI SMI Delay Timer.
Bit
Description
7
SYS_SMI_EN. 1=Enable (master enable for system events in the SYSEVNT[2:0] Registers).
0=Disable these system events from generating an SMI.
6
SWEXT_SMI_EN. 1=Enable software SMI# generated by bit 0 of this register. This bit (bit 6)
also enables the EXTSMI# signal to cause an SMI, if enabled in the SYSSMIE Register.
0=Disable these SMIs from generating an SMI.
5
Reserved.
4
LTRP_SMI_EN. 1=Enable (master enable for the local traps). 0=Disable (local traps will not
cause an SMI).
3
LSTBY_SMI_EN. 1=Enable (master enable for the standby timers). 0=Disable (standby timers
will not cause an SMI).
2
GSTBY_SMI_EN. 1=Enable (global standby timer is loaded with intial value, begins counting,
and generates an SMI when the counter expires). 0=Disable global standby timer.
1
SUSP_SMI_EN. 1=Enable (SRBTN# and BATLOW# generate an SMI, if individual enable is
set in the MISCSMIE Register). 0=Disable SRBTN# ane BATLOW# from generating an SMI.
52
PRELIMINARY