I82371MX Datasheet, PDF (77/133 Pages) Intel Corporation – INTEL 430MX PCISET 82371MX MOBILE PCI I/O IDE XCELERATOR (MPIIX)

E
82371MX (MPIIX)
3.3.3.7. OCW2—Operational Control Word 2 Register
Register Location:
Default Value:
Attribute:
INT CNTRL-1—020h
INT CNTRL-2—0A0h
Bit[4:0]=undefined, Bit[7:5]=001
Write Only
OCW2 controls both the Rotate Mode and the End of Interrupt Mode. Following a PCIRST or ICW initialization,
the controller enters the fully nested mode of operation. Both rotation mode and specific EOI mode are disabled
following initialization.
Bit
Description
7:5
Rotate and EOI Codes. R, SL, EOI – These three bits control the Rotate and End of Interrupt
modes and combinations of the two. A chart of these combinations is listed above under the bit
definition.
Bits [7:5] Function
001
Non-specific EOI command
011
Specific EOI Command
101
Rotate on Non-Specific EOI Command
100
Rotate in Auto EOI Mode (Set)
000
Rotate in Auto EOI Mode (Clear)
111
*Rotate on Specific EOI Command
110
*Set Priority Command
010
No Operation
* L0–L2 Are Used
4:3
OCW2 Select. Must be programmed to 00 selecting OCW2.
2:0
Interrupt Level Select (L2, L1, L0). L2, L1, and L0 determine the interrupt level acted upon when
the SL bit is active. A simple binary code, outlined above, selects the channel for the command to
act upon. When the SL bit is inactive, these bits do not have a defined function; programming L2,
L1 and L0 to 0 is sufficient in this case.
Bit [2:0] Interrupt Level
Bit [2:0] Interrupt Level
000
IRQ 0(8)
001
IRQ 1(9)
010
IRQ 2(10)
011
IRQ 3(11)
100
IRQ 4(12)
101
IRQ 5(13)
110
IRQ 6(14)
111
IRQ 7(15)
3.3.3.8. OCW3—Operational Control Word 3 Register
Register Location:
Default Value:
Attribute:
INT CNTRL-1—020h
INT CNTRL-2—0A0h
Bit[6,0]=0, Bit[7,4:2]=undefined, Bit[5,1]=1
Read/Write
OCW3 serves three important functions—Enable Special Mask Mode, Poll Mode control, and IRR/ISR register
read control.
Bit
Description
7
Reserved. Must be 0.
PRELIMINARY
77