I82371MX Datasheet, PDF (74/133 Pages) Intel Corporation – INTEL 430MX PCISET 82371MX MOBILE PCI I/O IDE XCELERATOR (MPIIX)

82371MX (MPIIX)
E
Bit
Description
7:0
Counter Port bit[x]. Each counter I/O port address is used to program the 16-bit Count Register.
The order of programming, either LSB only, MSB only, or LSB then MSB, is defined with the
Interval Counter Control Register at I/O port address 043h. The counter I/O port is also used to
read the current count from the Count Register, and return the status of the counter programming
following a Read Back Command.
3.3.3. INTERRUPT CONTROLLER REGISTERS
The MPIIX contains an ISA-compatible interrupt controller that incorporates the functionality of two 82C59
interrupt controllers. The interrupt registers control the operation of the interrupt controller and can be accessed
from the PCI Bus via PCI I/O space.
3.3.3.1. ICW1—Initialization Command Word 1 Register
Register Location:
Default Value:
Attribute:
INT CNTRL-1—020h
INT CNTRL-2—0A0h
All bits undefined
Write Only
A write to Initialization Command Word 1 starts the interrupt controller initialization sequence. Addresses 020h
and 0A0h are referred to as the base addresses of CNTRL-1 and CNTRL-2, respectively. An I/O write to the
CNTRL-1 or CNTRL-2 base address with bit 4 equal to 1 is interpreted as ICW1. For MPIIX-based ISA systems,
three I/O writes to "base address + 1" must follow the ICW1. The first write to "base address + 1" performs
ICW2, the second write performs ICW3, and the third write performs ICW4.
ICW1 starts the initialization sequence during which the following automatically occur:
1. The Interrupt Mask register is cleared.
2. IRQ7 input is assigned priority 7.
3. The slave mode address is set to 7.
4. Special Mask Mode is cleared and Status Read is set to IRR.
5. If IC4 was set to 0, then all functions selected by ICW4 are set to 0. However, ICW4 must be programmed in
the MPIIX implementation of this interrupt controller, and IC4 must be set to a 1.
Bit
Description
7:5 ICW/OCW select: These bits should be 000 when programming the MPIIX.
4
ICW/OCW select: Bit 4 must be a 1 to select ICW1. After the fixed initialization sequence to
ICW1, ICW2, ICW3, and ICW4, the controller base address is used to write to OCW2 and OCW3.
Bit 4 is a 0 on writes to these registers. A 1 on this bit at any time will force the interrupt controller
to interpret the write as an ICW1. The controller will then expect to see ICW2, ICW3, and ICW4.
3
Edge/Level Bank Select (LTIM): This bit is disabled. Its function is replaced by the Edge/Level
Triggered Control (ELCR) Registers.
2
ADI: Ignored for the MPIIX.
1
Single or Cascade (SNGL): This bit must be programmed to a 0.
0
ICW4 Write Required (IC4): This bit must be set to a 1.
74
PRELIMINARY