I82371MX Datasheet, PDF (113/133 Pages) Intel Corporation – INTEL 430MX PCISET 82371MX MOBILE PCI I/O IDE XCELERATOR (MPIIX)

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82371MX (MPIIX)
4.8.2.4. STPCLK Control State Machine
Power management software can implement 3 possible state machines as illustrated in the Figure 4.12.
1. The MPIIX Clock Throttling hardware can automatically assert and negate STPCLK# based on the desired
duty cycle set up in the STPCLKLT and the STPCLKHT Registers when the CLK_THROTTLE_EN bit is set
(CLKC Register). Once this process (inner ring) is started, no further setup is required to continue the low
frequency operation. If system activity is detected (Break Events), MPIIX negates STPCLK# immediately.
2. The first software controlled STPCLK# sequence (middle ring) is initiated by a read of APMC and enters the
Stop Grant state if the STPCLK_MODE bits are set to enable the Stop Grant state. The system remains in
the Stop Grant state until a Break Event occurs. Then the MPIIX negates the STPCLK# signal to the CPU.
3. The second software controlled STPCLK# sequence (outside ring) is similar to the previous sequence.
However, since the STPCLK_MODE bits are set to enable the Stop Clock state, MPIIX brings the CPU
down to the Stop Clock state by stopping the external clock (HCLK) to the CPU complex. The CPU remains
in this state until a Break Event occurs. Then the MPIIX must start the HCLK again and wait for the internal
CPU clock to start up before negating the STPCLK# signal to the CPU.
after 1 ms
delay
brk-evnt
STPCLK#=0
System Event
(reloads hi-tmr)
STPCLK#=1
lo-tmr
expire or
brk-evnt
hi-tmr
expire
APMC-rd
and
STPGNT mode
STPCLK#=0
APMC-rd
and
STPCLK mode
STPCLK#=0
STPCLK#=0
brk-evnt _STPCLK#=0
CPUCLK-gated
stp-grnt
Figure 14. STPCLK Control State Machine
PRELIMINARY
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