I82371MX Datasheet, PDF (114/133 Pages) Intel Corporation – INTEL 430MX PCISET 82371MX MOBILE PCI I/O IDE XCELERATOR (MPIIX)

82371MX (MPIIX)
E
4.8.2.5. Auto Clock Throttle (ACT) Feature
The Auto Clock Throttle mode is similar to the Clock Throttle mechanism but is designed to allow the use of
“clock throttle” and, at the same time, handle break events that require more time to complete than is allowed by
the STPCLK High Timer (programmed via the STPCLKHT register). The Auto Clock Throttle mechanism
provides 3 groups of events (Table 11) that can “break” out of the Stop Grant state: the STPCLKHT/STPCLKLT
timers, the Burst Clock Events (BSTCLKEE[6:0] register), or the Clock Throttle Break Events (CLKTHLBRKE
register). These can be considered “Short”, “Medium”, and “Long” bursts of time. When a break event occurs or
the STPCLK Low timer expires, the MPIIX negates STPCLK# to the CPU for the amount of time assigned to that
break event.
MPIIX negates the STPCLK# signal as soon as the STPCLK Low Timer has expired. Then MPIIX transitions
between the STPCLK High Timer state and the STPCLK Low timer state, according to the values programmed
into the STPCLKHT and STPCLKLT Registers until a break event occurs.
Table 11. Break Even Groups For Auto Clock Throttle
Break Event Group
Timer
Resolution
Count
CLKTHL_BRK Event Clock Throttle
4ms
Standby Timer
2 - 256
(or 32ms)
(2 - 256)
BSTCLK Event
Burst CLock Timer
32us
2 - 256
(throttle ratio timers)
STPCLK Low Timer
32us
2 - 256
STPCLK High Timer
32us
(*Minimum count is 2 or greater since actual value is ± 1 resolution.)
2 - 256
Min*
8 ms
(64 ms)
64 us
64 us
64 us
Max
1 sec
(8 sec)
8 ms
8 ms
8 ms
The Auto Clock Throttle Mode is enabled by setting ACT_MODE_EN bit in the Clock Control Register (offset
D4h). The MPIIX asserts the STPCLK# signal AFTER the Clock Throttle Standby timer expires. This is the
longest delay of the 3 timers groups. While the STPCLK# signal is asserted the CPU is in the Stop Grant Mode
since MPIIX continues to run the HCLKO signal. The break events for each group are listed in the Table 12.
Table 12. Auto Clock Throttle Break Events
Stop Break Events
STPBRKEx Register
Burst Clock Events
BSTCLKEE Register
Clock THRTL Break Events
CLKTHLBRKEE Register
IRQs
IRQs
IRQs
INTR
INTR
NMI
NMI
SMI#
SMI#
SMI#
EXTSMI#
EXTSMI#
EXTSMI#
COMRI#
COMRI#
COMRI#
BATLOW#
BATLOW#
SRBTN#
(see note:)
PHLDA#
EXTEVNT#
Fixed Peripheral Decode
Programmable I/O Decode
SRBTN#
PHLDA#
EXTEVNT#
Fixed Peripheral Decode
Programmable I/O Decode
Programmable Memory Decode
Programmable Memory Decode
Note: These “Stop Break” events only apply to the Stop Clock mode and the Clock Throttle mode
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PRELIMINARY