I82371MX Datasheet, PDF (38/133 Pages) Intel Corporation – INTEL 430MX PCISET 82371MX MOBILE PCI I/O IDE XCELERATOR (MPIIX)

82371MX (MPIIX)
E
3.2.19. PCIDMAE—PCI DMA ENABLE REGISTER
Address Offset:
Default Value:
Attribute:
80h
00h
Read/Write
This register selects, on a channel by channel basis, whether the device using the DMA channel is on the
Extended I/O Bus or PCI Bus (including proliferation of the PCI bus).
Bit
Description
7
PCI/Extended I/O Bus DMA CH 7 (PCICH7). 1=PCI Bus. 0=Extended I/O Bus.
6
PCI/Extended I/O Bus DMA CH 6 (PCICH6). 1=PCI Bus. 0=Extended I/O Bus.
5
PCI/Extended I/O Bus DMA CH 5 (PCICH5). 1=PCI Bus. 0=Extended I/O Bus.
4
Reserved.
3
PCI/Extended I/O Bus DMA CH 3 (PCICH3). 1=PCI Bus. 0=Extended I/O Bus.
2
PCI/Extended I/O Bus DMA CH 2 (PCICH2). 1=PCI Bus. 0=Extended I/O Bus.
1
PCI/Extended I/O Bus DMA CH 1 (PCICH1). 1=PCI Bus. 0=Extended I/O Bus.
0
PCI/Extended I/O Bus DMA CH 0 (PCICH0). 1=PCI Bus. 0=Extended I/O Bus.
3.2.20. PCIDMA[A,B]PCI DMA AND PCI DMA EXPANSION REGISTER
Address Offset:
Default Value:
Attribute:
88h (REQA#/GNTA#), 89h (REQB#/GNTB#)
08h (both)
Read/Write
The PCI DMA Expansion request lines (REQ[A,B]#/GNT[A,B]#) provide PCI DMA and PCI DMA expansion
support. The default value for the registers selects the request/grant signal to control a PCI DMA expansion
device using DMA channel 0.
Bit
Description
7:4
Reserved.
3
Expansion. This bit provides an ability to control multiple DMA channels through a single
request/grant field. When the expansion bit is set to 1, the expansion agent is required to pass the
channel number to the arbiter when requesting service using the PCI DMA expansion channel
passing protocol, thus making the DMA channel field a “don’t care”. The expansion hardware will
then route the agent’s REQ#/GNT# pair to the appropriate internal DMA DREQ/DACK# pair,
depending on the value of the channel number passed to it.
38
PRELIMINARY