I82371MX Datasheet, PDF (100/133 Pages) Intel Corporation – INTEL 430MX PCISET 82371MX MOBILE PCI I/O IDE XCELERATOR (MPIIX)

82371MX (MPIIX)
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or both, by setting the IDETIM[TIME0] and or IDETIM[TIME1] bits. Transactions targeting the other drive will use
compatible timing. The MPIIX snoops bit 4 of byte 6 of the ATA command block for the IDE connector. By
keeping a copy of the current drive bits, the correct transaction timing can be determined.
4.5.2.1. IORDY masking
The IORDY signal can be forced asserted on a drive by drive basis by setting the IDETIM[IE0] and IDETIM[IE1]
register bits.
4.5.2.2. PIO 32 bit IDE data port mode
If the 32-bit IDE data port mode is enabled, 32-bit accesses to the IDE data port address (default 01F0h primary
etc.) result in two back to back 16-bit transactions to IDE.
The 32-bit data port feature is enabled for ALL timings, not just enhanced timing. Note that for compatible timing
(mode 0), a Shutdown latency and Startup latency is incurred between the two halves of the requested Dword.
This guarantees that the mode 0 IDE device will see the chip selects deassert for at least two clocks in between
the two 16-bit reads. The 32-bit mode might speed up CD ROM drives incrementally since the CD ROM drives
cannot be used with prefetching.
4.6. Interval Timer
The MPIIX contains three counters that are equivalent to those found in the 82C54 programmable interval timer.
Each counter output provides a key system function. Counter 0 is connected to interrupt controller IRQ0 and
provides a system timer interrupt for a time-of-day, diskette time-out, or other system timing functions. Counter 1
output (typically used to generate refresh requests for the ISA bus ) is reflected in port 61h, bit 4. Counter 2
generates the tone for the speaker. The 14.31818 MHz counters normally use OSC as a clock source.
Counter 0, System Timer
This counter functions as the system timer by controlling the state of IRQ0 and is typically programmed for Mode
3 operation. The counter produces a square wave with a period equal to the product of the counter period (838
ns) and the initial count value. The counter loads the initial count value one counter period after software writes
the count value to the counter I/O address. The counter initially asserts IRQ0 and decrements the count value by
two each counter period. The counter negates IRQ0 when the count value reaches 0. It then reloads the initial
count value and again decrements the initial count value by two each counter period. The counter then asserts
IRQ0 when the count value reaches 0, reloads the initial count value, and repeats the cycle, alternately asserting
and negating IRQ0.
Counter 1, Refresh Request
This counter provides the refresh cycle toggle in port 61h bit 4 and is typically programmed for Mode 2 operation.
The counter negates the refresh cycle toggle bit for one counter period (838 ns) during each count cycle. The
initial count value is loaded one counter period after being written to the counter I/O address. The counter initially
sets the refresh cycle toggle, and negates it for 1 counter period when the count value reaches 1. The counter
then sets the refresh cycle toggle and continues counting from the initial count value.
Counter 2, Speaker Tone
This counter provides the speaker tone and is typically programmed for Mode 3 operation. The counter provides
a speaker frequency equal to the counter clock frequency (1.193 MHz) divided by the initial count value. The
speaker must be enabled by a write to port 061h (see NMI Status and Control ports).
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PRELIMINARY