I82371MX Datasheet, PDF (35/133 Pages) Intel Corporation – INTEL 430MX PCISET 82371MX MOBILE PCI I/O IDE XCELERATOR (MPIIX)

E
82371MX (MPIIX)
Bit
4
3
2
1
0
Description
Fast Timing Bank Drive Select 1 (TIME1). When TIME1=0, accesses to the data port of
the enabled I/O address range use the 16-bit compatible timing PCI local bus path.
When TIME1=1 and the currently selected drive (via a copy of bit 4 of 1x6h) is Drive 1, then
accesses to the data port of the enabled I/O address range use the fast timing bank PCI local
bus IDE path. Accesses to the data port use fast timing only if bit 7 of this register (DTE1) is
0. Accesses to all non-data ports of the enabled I/O address range use the 8-bit compatible
timing PCI local bus path.
Reserved.
Prefetch and Posting Enable (PPE0). 1=Enable prefetch and posting to the IDE data port
for drive 0. 0=Disable.
IORDY Sample Point Enable Drive Select 0 (IE0). When IE0=0, IORDY sampling is
disabled for Drive 0. The internal IORDY signal is forced asserted guaranteeing that IORDY
is sampled asserted at the first sample point as specified by the ISP field in this register.
When IE0=1 and the currently selected drive (via a copy of bit 4 of 1x6h) is Drive 0, all
accesses to the enabled I/O address range sample IORDY. The IORDY sample point is
specified by the ISP field in this register.
Fast Timing Bank Drive Select 0 (TIME0). When TIME0=0, accesses to the data port of
the enabled I/O address range use the 16-bit compatible timing PCI local bus path.
When TIME0=1 and the currently selected drive (via a copy of bit 4 of 1x6h) is Drive 0, then
accesses to the data port of the enabled I/O address range use the fast timing bank PCI local
bus IDE path. Accesses to the data port use fast timing only if bit 3 of this register (DTE0) is
0. Accesses to all non-data ports of the enabled I/O address range use the 8-bit compatible
timing PCI local bus path.
3.2.15. MIRQRC—MOTHERBOARD DEVICE IRQ ROUTE CONTROL REGISTER
Address Offset :
70h
Default Value:
80h
Attribute:
R/W
This register controls the routing of MIRQ to the IRQ inputs. MIRQ# can be routed to any one of 11 interrupts.
When a MIRQ line and a PIRQ# line are steered to the same interrupt, the device connected to the MIRQ line
must be set for active high, level interrupts. In this case, the corresponding interrupt pin is masked. Bit 6 of that
motherboard device IRA Route Control Register must be programmed to a 0.
Bit
Description
7
Interrupt Routing Enable: 0=Enable routing, 1=Disable routing.
6
MIRQ/IRQx Sharing Enable: 0=Disable sharing, 1=Enable sharing. When sharing is disabled
and bit 7 of this register is 0, the interrupt specified by bits [3:0] is masked. Interrupt sharing
should only be enabled when the device connected to the MIRQ line and the device connected to
the IRQ line both produce active high, level interrupts.
5:4
Reserved. Read as 0's.
PRELIMINARY
35