I82371MX Datasheet, PDF (88/133 Pages) Intel Corporation – INTEL 430MX PCISET 82371MX MOBILE PCI I/O IDE XCELERATOR (MPIIX)

82371MX (MPIIX)
E
The Extended I/O Bus interface also provides byte swap logic, I/O recovery support, wait-state generation,
SYSCLK generation, and standard ISA port 92h Fast A20Gate and Fast CPU INIT.
All PCI cycles intended for the Extended I/O bus are positively decoded to allow a docking station bridge to claim
subtractively decoded PCI cycles. There are 5 programmable I/O address ranges for positive decode special
function I/O ports (PAC[5:1] Registers).
Access to the enabled BIOS range generates the BIOSCS# signal, if enabled in the BIOS Enable Register. This
is an 8-bit memory access and it is the only memory access supported on the Extended I/O bus. Access to the
standard 8-bit Keyboard Controller port generates the KBCS# signal. Access to the standard 8-bit Real Time
Clock ports generates an RTCCS#, RTCALE.
When the Programmable Chip Select Address Range is enabled, any access to that range generates the PCS#
signal. This PCS# signal can be used as the output enable for the address and data isolation buffer to the PCS#
port. The SDIR signal is used to control the direction of the data transceiver. When the peripheral connected to
the PCS# port is powered down or not in use, the buffers are tri-stated.
The PCS# signal can also be generated (if enabled) for Programmable Address Ranges 1 and 2. This allows the
system designer to generate chip selects for up to 3 non-contiguous I/O ranges using simple address decoding.
MPIIX supports an audio interface by providing a steerable DMA REQ/ACK pair, a steerable interrupt and
decoding of the Audio chip ports. MPIIX supports Soundblaster Pro compatibility through the use of an external
audio chip.
MPIIX supports mulit-function I/O devices including 8-bit access to standard serial ports, parallel ports, and
Floppy Disk Controller. A dedicated DMA signal pair (DREQ2/DACK2#) is used for the Floppy Controller
interface.
4.3.1. EXTENDED I/O BUS CYCLES FOR MPIIX AS A MASTER (PCI MASTER INITIATED)
The Extended I/O Bus interface supports the following types of cycles:
• PCI master initiated I/O cycle to positively decoded peripherals.
• PCI master initiated I/O cycle to the IDE interface.
• PCI master initiated memory cycle to 256 Kbyte BIOS region only.
• DMA compatible cycles between PCI memory (include main system DRAM) and Extended I/O Bus I/O
• Enhanced DMA cycles between PCI memory and Extended I/O Bus I/O
The EIO bus supports only 8-bit I/O ports. If a multi-byte PCI access is performed to a device on the EIO bus,
the cycle will be assembled from (read) or disassembled to (write) the sequential addresses in the PCI cycle.
The MPIIX generates the Extended I/O Bus system clock (SYSCLK). SYSCLK is a divided down version of the
PCICLK and has a frequency of 7.5 or 8.33 MHz, depending on the PCICLK frequency. The clock divisor value
is determined according to the strapping options as described in the SYSCLK signal description. MPIIX has an
internal pull-up resistor that sets the default divisor to 4. (This resister is disabled after reset.) When MPIIX stops
the PCICLK, SYSCLK is also stopped.
The MPIIX adds wait-states to MPIIX master cycles (not including DMA) to the Extended I/O Bus, if IOCHRDY is
sampled active. Wait states will be added as long as IOCHRDY is negated. The MPIIX shortens MPIIX master
cycles (not including DMA) to the Extended I/O Bus, if ZEROWS# is sampled active. Note that, If IOCHRDY and
ZEROWS# are sampled active at the same time, IOCHRDY takes precedence and wait-states are added.
The I/O recovery mechanism in the MPIIX is used to add additional recovery delay between PCI Master
originated 8-bit I/O cycles to the Extended I/O Bus. See the EXRT Register description for details.
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PRELIMINARY