I82371MX Datasheet, PDF (30/133 Pages) Intel Corporation – INTEL 430MX PCISET 82371MX MOBILE PCI I/O IDE XCELERATOR (MPIIX)

82371MX (MPIIX)
3.2.7. HEDT—HEADER TYPE REGISTER
Address Offset:
Default Value:
Attribute:
0Eh
00h
Read Only
The HEDT Register identifies the MPIIX as a single-function device.
Bit
Description
7:0
Device Type (DEVICET): 00h=single-function device.
E
3.2.8. SPPE—SERIAL & PARALLEL PORT ENABLE REGISTER
Address Offset:
Default Value:
Attribute:
49h
00h
Read/Write
This register enables/disables accesses to the Serial Ports and Parallel Ports on the Extended I/O Bus.
Bit
Description
7
Reserved.
6
LPT3 Enable 1=Enable (forward PCI I/O accesses to 0278–027Fh and 0678–067Bh to the
Extended I/O Bus). 0=Disable (confine to PCI).
5
LPT2 Enable. 1=Enable (forward PCI I/O accesses to 0378–037Fh and 0778–077Bh to the
Extended I/O Bus). 0=Disable (confine to PCI).
4
LPT1 Enable. 1=Enable (forward PCI I/O accesses to 03BC–03BFh and 07BC–07BFh to the
Extended I/O Bus). 0=Disable (confine to PCI).
3
COM4 Enable. 1=Enable (forward PCI I/O accesses to 02E8h–02EFh to the Extended I/O
Bus). 0=Disable (confine to PCI).
2
COM3 Enable. 1=Enable (forward PCI I/O accesses to 03E8h–03EFh to the Extended I/O
Bus). 0=Disable (confine to PCI).
1
COM2 Enable. 1=Enable (forward PCI I/O accesses to 02F8h–02FFh to the Extended I/O
Bus). 0=Disable (confine to PCI).
0
COM1 Enable. 1=Enable (forward PCI I/O accesses to 03F8h–03FFh to the Extended I/O
Bus). 0=Disable (confine to PCI).
30
PRELIMINARY