I82371MX Datasheet, PDF (124/133 Pages) Intel Corporation – INTEL 430MX PCISET 82371MX MOBILE PCI I/O IDE XCELERATOR (MPIIX)

82371MX (MPIIX)
E
4.9. Reset Support
The MPIIX integrates the system reset logic for the system and generates CPURST, PCIRST#, and RSTDRV
during power up (PWROK) and when a hard reset is initiated through the RC register. CPURST is asserted for 2
mS after the assertion of PWROK and PCIRST# is asserted for 1 ms after the assertion of PWROK.
The following MPIIX signals interface directly to the processor:
- CPURST
- INIT
- INTR
- NMI
- IGNNE#
- SMI#
- STPCLK#
These signals are open drain so that external logic is not required for interface with the processors based on
3.3V technology which do no support 5V tolerant input buffers. During power-up these signals are driven low to
prevent problems associated with 5V/3.3V power sequencing.
Some PCI devices may drive 3.3 V friendly signals directly to 3.3 V devices that are not 5 V tolerant. If such
signals are powered from the 5 V supply, they must be driven low when PCIRST# is asserted. Some of these
signals may need to be driven high before CPURST is negated. PCIRST# is negated 1 to 2 ms before CPURST
to allow time for this to occur.
124
PRELIMINARY