I82371MX Datasheet, PDF (53/133 Pages) Intel Corporation – INTEL 430MX PCISET 82371MX MOBILE PCI I/O IDE XCELERATOR (MPIIX)

E
82371MX (MPIIX)
Bit
0
Description
SWEXT_SMI_EN_SW. This bit permits software to generate an SMI. 1=Enable
(Software/EXTSMI SMI Delay Timer is reloaded, starts counting, and generates an SMI when
the timer expires).
3.2.52. SYSSMIS—System SMI STATUS Register
Address Offset:
Default Value:
Attribute:
C6h
00h
Read/Write
This register indicates whether IRQ[12,8,4,3,1], EXTSMI#, or the software SMI (via bit 0 of the GSMIE Register)
generated the SMI. The MPIIX sets these bits to a 1 and software sets these bits to 0 by writing a 0 to the
individual bit(s). If the MPIIX is setting a bit to 1 at the same time that software is setting it to a 0, the bit is set to
1.
Bit
Description
7
Reserved.
6
SWEXT_STAT_SW. 1=Software SMI caused an SMI# (setting bit 0 in the GSMIE Register).
5
SWEXT_STAT_EXTSMI. 1=EXTSMI# signal caused an SMI#.
4
SYS_STAT_IRQ12. 1=IRQ12 caused an SMI#.
3
SYS_STAT_IRQ8. 1=IRQ8# caused an SMI#.
2
SYS_STAT_IRQ4. 1=IRQ4 caused an SMI#.
1
SYS_STAT_IRQ3. 1=IRQ3 caused an SMI#.
0
SYS_STAT_IRQ1. 1=IRQ1 caused an SMI#.
3.2.53. MISCSMIS—Miscellaneous SMI STATUS Register
Address Offset:
Default Value:
Attribute:
C7h
00h
Read/Write
This register indicates whether SRBTN# and BATLOW caused an SMI. The register also permits power
management software to provide status on whether the system is in global standby. Note that the MPIIX sets
bits [2,1] to a 1 and software sets these bits to 0 by writing a 0 to the individual bit(s). If the MPIIX is setting bits
[2,1] to 1 at the same time that software is setting the bit to a 0, the bit is set to 1.
Bit
Description
7:4
Reserved.
3
SYSTEM_IN_GSTBY. This bit is set and reset by software to indicate whether the system is in
Global Standby.
2
SUSP_STAT_SRBTN. 1=SRBTN# signal caused an SMI#.
1
SUSP_STAT_BATLOW. 1=BATLOW# signal caused an SMI#.
PRELIMINARY
53