I82371MX Datasheet, PDF (85/133 Pages) Intel Corporation – INTEL 430MX PCISET 82371MX MOBILE PCI I/O IDE XCELERATOR (MPIIX)

E
82371MX (MPIIX)
4.1.3. PERIPHERAL CHIP SELECTS
The MPIIX generates chip selects for PCI initiated cycles to the BIOS, keyboard controller and real time clock.
The MPIIX also generates a programmable chip select for a peripheral device and generates RTCALE (address
latch enable) for the RTC. The chip selects are generated combinatorially from the SA(15:0) bus.
Table 3 lists the I/O and memory addresses that are positively decoded by MPIIX and, where applicable, shows
the corresponding chip select generation. Chip selects and optional address ranges can be enabled/disabled
through their corresponding configuration register. In general, the addresses shown in the table do not reside in
the MPIIX itself. Addresses 60h and 70h are exceptions since particular bits from these registers reside in the
MPIIX.
Address
0060h, 62h, 64h, 66h
70h, 72h, 74h, 76h
0071h, 73h, 75h, 77h
0201h
02x0–02xFh
0388–038Bh
03BC–03BFh,
07BC–07BEh
0378–037Fh,
0778–077Ah
0278–027Fh,
0678–067Ah
03F8–03FFh
02F8–02FFh
03E8–03EFh
02E8–02EFh
03F0–03F5h, 03F7h
0370–0375h, 0377h
03F6h
0376h
ADDR (10-bit)
ADDR + MASK
ADDR + MASK
ADDR + MASK
ADDR + MASK
ADDR + MASK
ADDR + MASK
Table 3. Extended I/O Bus Decode
Type
Name
R/W
Keyboard Controller
W
Real Time Clock Address
R/W
Real Time Clock Data
R/W
Audio Port
R/W
Audio Port x = 2, 3, 4, or 5
R/W
Audio Port
Parallel Port, LPT1 or EPP/ECP
Parallel Port, LPT2 or EPP/ECP
Parallel Port, LPT3 or EPP/ECP
R/W
Serial Port, COM1
R/W
Serial Port, COM2
R/W
Serial Port, COM3
R/W
Serial Port, COM4
R/W
FDC Primary
R/W
FDC Secondary
R/W
IDE Primary
R/W
IDE Secondary
R/W
I/O Config Address (2-byte range)
R/W
Prog Chip Select PCS#
R/W
Prog I/O Range #1
R/W
Prog I/O Range #2
R/W
Prog I/O Range #3
R/W
Prog I/O Range #4
R/W
Prog I/O Range #5
Encoded Chip
Select
KBCCS#
RTCALE#
RTCCS#
PCS#
PRELIMINARY
85