I82371MX Datasheet, PDF (58/133 Pages) Intel Corporation – INTEL 430MX PCISET 82371MX MOBILE PCI I/O IDE XCELERATOR (MPIIX)

82371MX (MPIIX)
E
3.2.62. CLKC—Clock Control Register
Address Offset:
Default Value:
Attribute:
D4h
00h
Read/Write
This register enables the PCICLK to be stopped and enables clock throttling. The register also permits software
to control STPCLK#.
Bit
Description
7
Clock Throttle Standby Timer Frequency (CLKTHSBYT) Timer: This bit selescts the
resolution (granularity) of the 8-bit CLKTHSBYT. 0 = 4 ms, 1 = 32 ms.
6:5
Reserved.
4
Auto Clock Throttle (ACT_MODE_EN): 1=Enable. 0=Disable.
3:2
STPCLK_MODE. When either bit is set to 1, a read from the APMC Register causes
STPCLK# to be asserted. When bits [3:2]=00, reads from the APMC Register have no effect on
the STPCLK# function.
Bits[3:2]
Function
00
Disable STPCLK# function
01
Enable Stop Grant Mode
10
Enable Stop Clock Mode
11
Reserved
1
CLK_THROTTLE_EN. 1=Enable clock throttling. 0=Disable clock throttling.
0
PCI_CLK_CTRL_EN. 1=Enable (PCI clock can be stopped). 0=Disable.
3.2.63. STPCLKLT—STPCLK# Low Timer Register
Address Offset:
Default Value:
Attribute:
D6h
00h
Read/Write
The value in this register defines the duration of the STPCLK# asserted period when bit 1 in the CLKC Register
is set to 1. The value in this register is loaded into the STPCLK# Timer when STPCLK# is asserted. The
STPCLK# timer counts using a 32-us clock with a range of 32 µs to 8 ms.
Bit
Description
7:0
STPCLK_LO_TMR. Bits [7:0] define the duration of the STPCLK# asserted period during clock
throttling. 00h is an illegal programmed count.
58
PRELIMINARY