I82371MX Datasheet, PDF (79/133 Pages) Intel Corporation – INTEL 430MX PCISET 82371MX MOBILE PCI I/O IDE XCELERATOR (MPIIX)

E
82371MX (MPIIX)
3.3.3.10. ELCR2—Edge/Level Triggered Register
Register Location:
Default Value:
Attribute:
INT CNTRL-2—4D1h
00h
Read/Write
ELCR2 register allows IRQ[15,14,12:9] to be edge or level programmable on an interrupt by interrupt basis. Note
that, IRQ[13,8#] are not programmable and are always edge sensitive.
Bit
Description
7
IRQ15 ECL: 0 = edge triggered mode; 1 = level sensitive mode.
6
IRQ14 ECL: 0 = edge triggered mode; 1 = level sensitive mode.
5
Reserved: Must be 0.
4
IRQ12 ECL: 0 = edge triggered mode; 1 = level sensitive mode.
3
IRQ11 ECL: 0 = edge triggered mode; 1 = level sensitive mode.
2
IRQ10 ECL: 0 = edge triggered mode; 1 = level sensitive mode.
1
IRQ9 ECL: 0 = edge triggered mode; 1 = level sensitive mode.
0
Reserved: Must be 0.
3.3.4. RESET EXTENDED I/O-BUS IRQ12 AND IRQ1 REGISTER
Register Location:
Default Value:
Attribute:
60h
N/A
Read only
This register clears the mouse interrupt function and the keyboard interrupt (IRQ1). Reads to this address are
monitored by the MPIIX. When the mouse interrupt function is enabled (FDC Enable Register), the mouse
interrupt function is provided on the IRQ12/M input signal. In this mode, a mouse interrupt generates an interrupt
through IRQ12 to the Host CPU. A read of 60h releases IRQ12. Reads/writes flow through to the Extended I/O
Bus. A read of this address always clears the keyboard interrupt (IRQ1).
Bit
Description
7:0
Reset IRQ12 and IRQ1. No specific pattern. A read of address 60h executes the command.
PRELIMINARY
79