I82371MX Datasheet, PDF (57/133 Pages) Intel Corporation – INTEL 430MX PCISET 82371MX MOBILE PCI I/O IDE XCELERATOR (MPIIX)

E
82371MX (MPIIX)
3.2.60. SYSEVNTE2—System EVENT Enable 2 Register
Address Offset:
Default Value:
Attribute:
D2h
00h
Read/Write
This register enables hardware events as system events for power management control. This register also
contains a master enable for all system events.
Bit
Description
7
SYS_EVNT_EN_HWSUS. 1=Enable BATLOW# and SRBTN# as a System Event. The
corresponding BATLOW# and SRBTN# enable bits must be set to 1 in the MISCSMIE Register
for these signals to be recognized as system events.
6
SYS_EVNT_EN_EXTSMI. 1=Enable EXTSMI# as a System Event. The EXTSMI# bit must be
set to 1 in the SYSSMIE Register for this signal to be recognized as a system event.
5
SYS_EVNT_EN_SMI. 1=Enable SMI# as a System Event.
4
SYS_EVNT_EN_NMI. 1=Enables NMI as a System Event.
3
SYS_EVNT_EN_INTR. 1=Enable INTR as a System Event.
2
Reserved.
1
SYS_EVNT_EN_COMRI. 1=Enable COMRI# as a System Event.
0
SYS_EVNT_EN. 1=Enable System Events (each System Event is individually enabled via
SYSEVNT[2:0]). 0=Disable all System Events. An enabled system event causes the Global
Standby Timer and the SMI Delay timers to be reloaded.
3.2.61. BSTCLKT — Burst Count Timer Register
Address Offset:
Default Value:
Attribute:
D3h
00h
Read/Write
This register provides the 8-bit initial count for the Burst Count Timer that controls the STPCLK# negation period
after a Burst Clock Event in ACT mode. The timer runs with the granularity of 32 µs giving the timer the range of
32 µs to 8 ms. The timer is reloaded from this register every time an enabled Burst Clock Event is detected.
STPCLK# is asserted when the timer expires.
Bit
Description
7:0
STPCLK_LO_TMR. This field contains the Burst Count Timer count value.
PRELIMINARY
57