I82371MX Datasheet, PDF (106/133 Pages) Intel Corporation – INTEL 430MX PCISET 82371MX MOBILE PCI I/O IDE XCELERATOR (MPIIX)

82371MX (MPIIX)
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4.8.1. SMI GENERATION
SMI# Generation logic controls the enabling of the SMI# sources, the timing and assertion of the SMI# signal to
the CPU, and the recording of what event triggered SMI#.
• SMI# Sources: SMI# is generated periodically for system polling or specifically in response to a change in
the system’s power management requirements. These changes can be signaled by the Local Standby
hardware, Global Standby Idle Timer expiration, specific software SMI# requests such as writes to the
Advanced Power Management port (APMC) or the software SMI request, the external SMI# signal
(EXTSMI#), specific hardware SMI# requests such as the suspend/resume button (SRBTN#), or the Battery
Low signal (BATTLOW#).
Note: Local Standby is discussed in more detail in a separate section. SRBTN# and BATLOW# are
discussed in the Suspend section. All other SMI sources will be discussed in this section.
• SMI# Enables: All of the SMI# sources have individual enables. Some sources have group enables that
minimize the time necessary to block SMI# during certain power management procedures. The global SMI#
Enable bit (SMI_EN) in the SYSMGNTC Register prevents any SMI# source from setting it’s corresponding
SMI# status bit.
• SMI# Request Status: The SMI# sources have a corresponding request status bit structure which allows
the SMI handler to quickly vector to the appropriate subroutine.
• SMI# Signal Generation: SMI# will remain asserted as long as the SMI_GATE is set to 1 (SYSMGNTC
Register). SMI# is negated when the SMI_GATE bit is set to 0. SMI# is asserted again when SMI_GATE is
set to 1, if any SMIs are pending. Access to a powered-down peripheral requires a special sequence
(“synchronous SMI#”) so that the CPU can restart the cycle to that device after it is returned to full power.
4.8.1.1. SMI Enables
MPIIX has one global SMI# enable that, when disabled, blocks all SMI# sources and when enabled allows
individual enable control. Each SMI# source has its own individual enable bit while some groups of SMI#
sources have group enables. When a 1 is written to the enable, the source or group is enabled. When a 0 is
written to the enable, the source or group is disabled.
If the SMI# source is associated with a timer, setting the SMI# enable bit will generally initiate the timer count-
down. If the SMI# source is associated with an access trap, setting the enable bit will enable the access trap.
The specific mechanisms are described in more detail in the specific SMI# source section.
4.8.1.2. SMI Request Status
The request status bits correspond directly to the SMI event that needs servicing. When an SMI event occurs,
the hardware automatically sets the corresponding request status bit(s) to a 1 for the event that caused the SMI.
The status bits are cleared by writing 0 to them. Only the hardware can set status bits to 1. In the event that the
hardware is trying to set the bit to a 1 at the same time that it is being cleared, the hardware set to 1 will
dominate. The SMI handler will query the status bits to see what caused the SMI and then branch to the
appropriate routine. As the individual routines complete they reset the appropriate status bit by writing a 0 to the
corresponding bit.
The first column of Table 9 lists the bits that are used to enable the SMI# sources. The specific function of each
of the enables is described in the corresponding section for that SMI# source. The second column lists the
status bit for each of the SMI# sources.
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PRELIMINARY