I82371MX Datasheet, PDF (15/133 Pages) Intel Corporation – INTEL 430MX PCISET 82371MX MOBILE PCI I/O IDE XCELERATOR (MPIIX)

E
82371MX (MPIIX)
Signal Name
MEMW#
ZEROWS#
SD[7:0]/
DD[7:0]
SDIR
Type
O
5V
TTL
8mA
I
5V
st
pu8KΩ
TTL
I/O
5V
pu8KΩ
TTL
8mA
O
5V
TTL
4mA
PCIRST#
High
Tri-state
Low
Description
MEMORY WRITE: MEMW# is the command to the BIOS
memory that it may latch data from the Extended I/O data
bus.
ZERO WAIT STATES: An Extended I/O Bus slave asserts
ZEROWS# after its address and command signals have
been decoded to indicate that the current cycle can be
shortened. An 8-bit ISA memory cycle can be reduced to
three SYSCLKs.
SYSTEM DATA: SD[7:0] provide the 8-bit data path for
devices residing on the Extended I/O Bus. The MPIIX tri-
states these signals during PCIRST#.
SYSTEM ADDRESS TRANSCEIVER DIRECTION: This
signal controls the direction of the '245 transceivers that
interface the DD[15:0] signals to the SA[15:8] and SD[7:0]
signals. Default condition is high (transmit).
2.4. Motherboard I/O Device Interface Signals
Signal Name
Type
PCIRST#
Description
SA17/
PCS#
O
5V
TTL
8mA
Undefined
PROGRAMMABLE CHIP SELECT. PCS# is asserted
for Extended I/O Bus I/O cycles that are generated by
PCI masters, if the access is in the address range
programmed into the PCSC Register. The Extended I/O
Bus buffer signals are enabled when the chip select is
asserted (i.e., it is assumed that the peripheral that is
selected via this pin resides on the Extended I/O Bus).
PCS# can be used to control the isolation buffer to the
Plug-n-Play port isolation buffer.
BIOSCS#
O
5V
TTL
4mA
Undefined
BIOS CHIP SELECT: BIOSCS# is asserted during read
or write accesses to BIOS. BIOSCS# is driven
combinatorially from the Extended I/O Bus addresses
SA[17:0], except during DMA. During DMA cycles,
BIOSCS# is not generated.
KBCS#
O
5V
TTL
4mA
Undefined
KEYBOARD CONTROLLER CHIP SELECT: KBCS# is
asserted during I/O read or write accesses to KBC
locations 60h, 62h, 64h, and 66h. For DMA cycles,
KBCS# is never asserted.
SA16/
RTCCS#
O
5V
TTL
8mA
Undefined
REAL TIME CLOCK CHIP SELECT: RTCCS# is
asserted during read or write accesses to RTC location
71h, 73h, 75h, and 77h. RTCCS# can be tied to a pair of
external OR gates to generate the real time clock read
and write command signals.
PRELIMINARY
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