I82371MX Datasheet, PDF (66/133 Pages) Intel Corporation – INTEL 430MX PCISET 82371MX MOBILE PCI I/O IDE XCELERATOR (MPIIX)

82371MX (MPIIX)
E
Bit
Description
3:2 DMA Transfer Type: When Bits [7:6]=11, the transfer type bits are irrelevant.
Bits[3:2]
00
01
10
11
Transfer Type
Verify transfer
Write transfer
Read transfer
Illegal
1:0 DMA Channel Select: Bits [1:0] select the DMA Channel Mode Register written to by bits [7:2].
Bits[1:0]
00
01
10
11
Channel
Channel 0 (4)
Channel 1 (5)
Channel 2 (6)
Channel 3 (7)
3.3.1.3. DR—DMA Request Register
Register Location:
Default Value:
Attribute:
Channels 0−3—09h
Channels 4−7—0D2h
Reserved
Write Only
Writes to these register address locations are claimed by the MPIIX but have no effect.
Bit
Description
7:3
Reserved. Must be 0.
2
DMA Channel Service Request. Reserved.
1:0
DMA Channel Select. Reserved.
3.3.1.4. Mask Register—Write Single Mask Bit
Register Location:
Default Value:
Attribute:
Channels 0−3—0Ah
Channels 4−7—0D4h
Bits[1:0]=undefined, Bit 2=1, Bits[7:3]=0
Write Only
A channel's mask bit is automatically set when the Current Byte/Word Count Register reaches terminal count
(unless the channel is programmed for autoinitialization). Setting the entire register disables all DMA requests
until a clear mask register instruction allows them to occur. This instruction format is similar to the format used
with the DMA Request Register. Masking DMA channel 4 (DMA controller 2, channel 0) also masks DMA
channels [3:0]. The fields in this register are set to 1 following a PCIRST or Master Clear.
Bit
Description
7:3
Reserved. Must be 0.
2
Channel Mask Select. 1=Disable DREQ for the selected channel. 0=Enable DREQ for the
selected channel.
66
PRELIMINARY