I82371MX Datasheet, PDF (69/133 Pages) Intel Corporation – INTEL 430MX PCISET 82371MX MOBILE PCI I/O IDE XCELERATOR (MPIIX)

E
82371MX (MPIIX)
3.3.1.8. DMA Base and Current Byte/Word Count Registers (Compatible Segment)
Register Location:
Attribute:
DMA Channel 0—001h
DMA Channel 1—003h
DMA Channel 2—005h
DMA Channel 3—007h
Default Value: Undefined
Read/Write
DMA Channel 4—0C2h
DMA Channel 5—0C6h
DMA Channel 6—0CAh
DMA Channel 7—0CEh
This register determines the number of transfers to be performed. The actual number of transfers is one more
than the number programmed in the Current Byte/Word Count Register When the value in the register is
decremented from zero to FFFFh, a TC is generated. After an autoinitialization, this register retains the original
programmed value. Autoinitialize can only occur when a TC occurs. If it is not autoinitialized, this register has a
count of FFFFh after TC.
For transfers to/from an 8-bit I/O, the Byte/Word count indicates the number of bytes to be transferred. This
applies to DMA channels 0-3. For transfers to/from a 16-bit I/O, with shifted address, the Byte/Word count
indicates the number of 16-bit words to be transferred. This applies to DMA channels 5−7.
Bit
Description
15:0
Base and Current Byte/ Word Count. This field represents the 16-byte/word count bits used
when counting down a DMA transfer. Upon PCIRST or Master Clear, the value of these bits is
undefined.
3.3.1.9. DMA Memory Low Page Registers
Register Location:
Access:
DMA Channel 0—087h
DMA Channel 1—083h
DMA Channel 2—081h
DMA Channel 3—082h
Default Value: Undefined
Read/Write
DMA Channel 5—08Bh
DMA Channel 6—089h
DMA Channel 7—08Ah
Each channel has an 8-bit Low Page Register. The DMA memory Low Page Register contains bits 23–16 of the
24-bit address. The register works in conjunction with the DMA controller's Current Address Register to define
the complete (24-bit) address for the DMA channel. This 8-bit register is read or written directly. This register is
static throughout the DMA transfer. Following an autoinitialization, this register retains the original programmed
value. Autoinitialize takes place only after a TC.
Bit
Description
7:0 DMA Low Page [23:16]. These bits represent address bits [23:16] of the 24-bit DMA address.
Upon PCIRST or Master Clear, the value of these bits is undefined.
PRELIMINARY
69