I82371MX Datasheet, PDF (93/133 Pages) Intel Corporation – INTEL 430MX PCISET 82371MX MOBILE PCI I/O IDE XCELERATOR (MPIIX)

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82371MX (MPIIX)
DMA Cycle Type
Normal
Normal TC
Verify
Verify TC
Table 4. DMA Cycle vs I/O Address
DMA I/O Address
TC (A2)
00h
0
04h
1
0C0h
0
0C4h
1
PCI Cycle Type
I/O Read/Write
I/O Read/Write
I/O Read
I/O Read
For PCI DMA cycles, the I/O address indicates the type of DMA cycle taking place (whether its a normal or a
verify cycle and if the cycle is the last transfer of the buffer). Note that the A2 address line is encoded as the
terminal count signal for PCI cycles. A2 is asserted during a PCI I/O cycle to indicate the last DMA transfer. To
ensure that non Mobile PC/PCI compliant PCI I/O devices do not confuse Mobile PC/PCI DMA cycles for normal
I/O cycles, the addresses used by the PCI DMA cycles correspond to the slave addresses of the Mobile PC/PCI
DMA controller.
All PCI DMA I/O ports must be dword aligned and can be either byte or word in size. Thus, PCI DMA I/O ports
must always be connected to the lower data lines of the PCI data bus (Table 5). The byte enables also reflect
the cycle width during the I/O portion of a PCI DMA cycle (Table 6).
Table 5. PCI Data Bus vs DMA I/O Port Size
PCI DMA I/O Port Size
PCI Data Bus Connection
byte
AD[7:0]
word
AD[15:0]
Table 6. DMA I/O Cycle Width vs BE[3:0]#
BE[3:0]#
Description
1110b
8-bit DMA I/O Cycle
1100b
16-bit DMA I/O Cycle
NOTE: For verify cycles, BE[3:0]# are “don’t cares”.
Every DMA device (including secondary bus arbiters) must recognize a valid signal on its GNT# combined with
the DMA I/O address as its command authorization to initiate a DMA access cycle. MPIIX asserts the DMA I/O
device's GNT# signal until the data phase of the I/O portion of the DMA transfer. Note that the AC timings for the
I/O portion of a PCI DMA cycle are identical to the timings outlined in the PCI revision 2.0 specification for PCI
I/O cycles.
PRELIMINARY
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