I82371MX Datasheet, PDF (43/133 Pages) Intel Corporation – INTEL 430MX PCISET 82371MX MOBILE PCI I/O IDE XCELERATOR (MPIIX)

E
82371MX (MPIIX)
3.2.29. PAMC—PROGRAMMABLE ADDRESS MASK C REGISTER
Address Offset:
Default Value:
Attribute:
A4h
00h
Read/Write
This register selects an address range of 1, 2, 4, 8, or 16 bytes (split range is precluded) for the Programmable
Address Control Registers (PAC[5,4]).
Bit
Description
7:4
Programmable Address Control 5 Mask (PAC5MASK). 1=corresponding address bit is not
used in the address decode. 0=Corresponding address bit is used in the address decode. For
example, mask field=0011 selects a 4-byte range.
3:0
Programmable Address Control 4 Mask (PAC4MASK). 1=corresponding address bit is not
used in the address decode. 0=Corresponding address bit is used in the address decode. For
example, mask field=0011 selects a 4-byte range.
3.2.30. PADE[2:0]—PERIPHERAL ACCESS DETECT ENABLE REGISTERS
Address Offset:
Default Value:
Attribute:
A5hPADE0, A6hPADE1, A7hPADE2
00h
Read/Write
This register enables the addresses used to assert the PAD# signal. Setting the bits to 1 enables the
corresponding memory or IO address to be part of the peripheral activity detection range. If a PCI address is
detected in the enabled peripheral activity range, the MPIIX asserts the Peripheral Access Detect (PAD#) signal.
Setting the bit to 0 disables this function. Tables 16 and 17 (Section 4.8) provide the address range for where the
associated function is determined.
Bits
PADE2
PADE1
PADE0
7
Audio-E.
COM4.
PMAC1.
6
Audio-D.
COM3.
PMAC0.
5
Audio-C.
COM2.
PAC5.
4
Audio-B.
COM1.
PAC4.
3
Audio-A.
FDC, Secondary Drive.
PAC3.
2
Parallel Port 3.
FDC, Primary Drive.
PAC2.
1
Parallel Port 2.
IDE, Secondary Drive.
PAC1.
0
Parallel Port 1.
IDE, Primary Drive.
PCSC.
PRELIMINARY
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