I82371MX Datasheet, PDF (109/133 Pages) Intel Corporation – INTEL 430MX PCISET 82371MX MOBILE PCI I/O IDE XCELERATOR (MPIIX)

E
82371MX (MPIIX)
External Hardware SMI (EXTSMI#) and Software SMI#
Both of these SMI# sources can be disabled (by the SWEXT_SMI_EN bit to 0 in the GSMIE Register). When
SWEXT_SMI_EN=1, the individual SMI enables determine if the source is enabled.
This hardware EXTSMI# signal and the software SMI# might require a delay to allow the system to settle prior to
asserting the SMI# signal to the CPU. Both sources share an SMI# delay timer (Software/EXTSMI# SMI Delay
Timer) that allows the system to finish its current bus master or docking station bridge actvity before the SMI# is
generated.
EXTSMI#
The external SMI input signal (EXTSMI#) permits hardware to generate an SMI# to the CPU. Power
management software can enable this SMI# source (by setting the SWEXT_SMI_EN_EXTSMI bit to a 1 in the
SYSSMIE Register). When an EXTSMI# input is asserted, the SMI# request is passed to the
Software/EXTSMI# SMI Delay Timer and the timer begins to count down. The EXTSMI# signal is level triggered
and should be asserted for a minimum of 32 usec. The EXTSMI# signal is typically asserted until it is cleared by
the SMI# interrupt handler routine.
SW SMI#
Software can generate an SMI# to invoke the SMI# handler by setting the SWEXT_SMI_EN_SW bit to a 1 in the
GSMIE Register. This SMI# request is passed to the Software/EXTSMI# SMI Delay Timer and the timer begins
to count down.
SWEXT SMI# Delay Timer
The Software/EXTSMI# SMI Delay Timer is loaded by software with an 8-bit count for a minimum delay of 1 ms
to a maximum delay of 255 ms. This delay timer begins counting down when the software SMI# enable bit is set
(SWEXT_SMI_EN) or when the EXTSMI# input is asserted by the system (and the SWEXT_SMI_EN_EXTSMI
bit was previously enabled).
The Software/EXTSMI# SMI Delay Timer is reloaded by the system events that are enabled. (These are the
same system events that reload the Global Standby Timer). When the timer expires it will generate an SMI#, if
enabled. When the SMI# request is generated, the MPIIX sets the SMI# group request status bit
(SWEXT_STAT in the GSMIS Register). The MPIIX also sets the individual status bit (SYSSMIS Register) for
the source that caused the SMI# or sets the status bit for both sources, if both become active while the SMI#
delay timer is counting down.
APM Ports
The APM ports consist of two 8-bit portsA status port (APMS Register) and a control port (APMC Register).
These read/write registers are used to transfer information between the OS and the SMI handler. The APMS
Register resides at system I/O address 0B3h and the APMC Register at 0B2h. I/O writes to these registers store
data in them. I/O reads return data from these registers.
The MPIIX positively decodes PCI accesses to B2h and B3h. Read data is returned from the internal MPIIX
register. Extended I/O masters can not access B2h and B3h.
I/O writes to the APMC Register generates an SMI if the APM_SMI_EN bit is set to 1 (see SYSSMIE Register).
MPIIX also supports the APM CallBack feature where the SMI# is routed to one of the PCI interrupts (PIRQA),
instead of the SMI# interrupt. This PIRQA interrupt can then be routed to any of the internal IRQs. The APM
CallBack feature is enabled when the APM_CALLBACK_EN bit is set to 1 (MISCSMIE Register) and the
APM_SMI_EN bit is set to 1 (SYSSMIE Register) and the AMP_SMI_EN bit is set to 1. When either the APM
SMI# or the APM callBack to PIRQA# occurs, the APM_STAT bit in the GSMIS Register is set to 1. The
interrupt handler should clear the APM_STAT bit before returning.
PRELIMINARY
109