I82371MX Datasheet, PDF (96/133 Pages) Intel Corporation – INTEL 430MX PCISET 82371MX MOBILE PCI I/O IDE XCELERATOR (MPIIX)

82371MX (MPIIX)
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4.4.4.5. Verify DMA Cycle
The verify DMA cycle is similar to the normal DMA cycle, except no memory portion of the cycle takes place,
and the I/O portion has the attributes of an I/O read cycle with address of 0C0h (Figure 7). Data is not
transferred during a verify DMA cycle.
Note that some ISA DMA devices require that the DACK# toggle for each verify cycle. The PCI protocol,
however, does not toggle GNT# for each transfer, but can perform multiple verify cycles while GNT# remains
active. Bridges to ISA type peripherals should decode the verify cycle such that the GNT# to DACK# translation
causes the DACK# to toggle for each transfer. This is only necessary on verify cycle (not normal DMA cycles).
P C IC LK
R E Q[x]#
GN T[x]#
A D [31 :0 ]
C /B E [3 :0]#
FRAME#
IR D Y #
TRDY#
Ve rify C y c le
C locks not to scale
R E Q S erial P roto col (9 C lo cks )
C lo ck s n o t to sca le
G N T S erial P rotoc ol (4 C lock s)
C0h
02h
FFh
V erify C ycle
C 0h
02h
FFh
052507
Figure 7. Verify DMA Cycle
96
PRELIMINARY