I82371MX Datasheet, PDF (14/133 Pages) Intel Corporation – INTEL 430MX PCISET 82371MX MOBILE PCI I/O IDE XCELERATOR (MPIIX)

82371MX (MPIIX)
E
2.3. Extended I/O Bus Signals
Signal Name
Type
PCIRST#
SYSCLK
O
5V
TTL
8mA
Active
IOCHRDY
I
5V
pu8KΩ
IOR#
IOW#
SA[7:0],
DCS1#,
DCS3#,
DA[2:0]
SA[15:8]/
DD[15:8]/
SD[15:8]
SA[17,16],
PCS#,
RTCCS#
SD[15:8]/
DD[15:8]/
SA[15:8]
MEMR#
O
5V
TTL
8mA
O
5V
TTL
8mA
O
5V
TTL
8mA
O
O
5V
I/O
5V
O
5V
TTL
8mA
High
High
Undefined
Undefined
Undefined
Undefined
High
Description
SYSTEM CLOCK: SYSCLK is the reference clock for the
Extended I/O Bus and drives the bus directly. SYSCLK is
generated by dividing PCICLK by 3 or 4. The SYSCLK
frequencies supported are 6.25 MHz, 7.5 MHz and 8.33 MHz.
SYSCLK is a divided down version of PCICLK.
Hardware strapping option
SYSCLK is tri-stated when PWROK is negated. The value of
SYSCLK is sampled on the assertion of PWROK: If sampled
low, the ISA clock divisor is 3 (for 25 MHz PCI). Otherwise,
the divisor is 4 (for 30 MHz PCI). The default value (divide-
by-4) is determined by an internal pull-up resistor (50 KΩ).
This pullup is disabled after reset.
I/O CHANNEL READY: Resources on the Extended I/O Bus
negate IOCHRDY to indicate that additional time (wait-states)
is required to complete the cycle. This signal is normally high.
IOCHRDY is an input when the MPIIX owns the Extended I/O
Bus and the CPU or a PCI agent is accessing an Extended
I/O slave or during DMA transfers.
I/O READ: IOR# is the command to an Extended I/O Bus
slave device that the slave may drive data on the Extended
I/O data bus (SD[15:0]).
I/O WRITE: IOW# is the command to an Extended I/O Bus
slave device that the slave may latch data from the Extended
I/O data bus (SD[15:0]).
SYSTEM ADDRESS BUS: These address output signals
define the selection with the granularity of one byte. For I/O
accesses, only SA[15:0] are used. SA[17:0] are outputs
during memory cycles to the Extended I/O Bus BIOS range.
SA[17:0] are at an unknown state during PCIRST#. SA[15:0]
are driven to 0 durintg DMA cycles to the Extended I/O Bus.
SA[17:16] are driven to 1 following PCIRST# and during DMA
cycles to the Extended I/O Bus.
SYSTEM DATA BUS: SD[15:8] provide the higher byte of
the data path to DMA devices residing on the Extended I/O
Bus. SD[15:8] are not available to memory or I/O devices on
the Extended I/O Bus.
MEMORY READ: MEMR# is the command to the BIOS
memory that it may drive data onto the Extended I/O data
bus.
14
PRELIMINARY