I82371MX Datasheet, PDF (32/133 Pages) Intel Corporation – INTEL 430MX PCISET 82371MX MOBILE PCI I/O IDE XCELERATOR (MPIIX)

82371MX (MPIIX)
E
Bit
Description
4
Lower BIOS CS# Enable 0. When bit=1 (enabled), PCI master accesses to locations 0E0000h–
000E3FFFh (and alias at 4G) generate BIOSCS#. This region is also used for Kanji BIOS. When
bit 4=0, the MPIIX does not generate BIOSCS#.
3
F-SEGMENT BIOS ENABLE: 1=Enable (default). 0=Disable. This bit enables the MPIIX to claim
cycles to the F-Segment BIOS. When disabled, MPIIX does not claim these cycles. MPIIX
should be programmed to NOT claim cycles to the F-Segment BIOS after the DRAM controller is
set to claim PCI cycles to the shadowed F-Segment.
2
BIOSCS# Write Protect. When bit 2=1 (enabled), BIOSCS# is asserted for BIOS memory read
and write cycles in the decoded BIOS region. When bit 2=0, BIOSCS# is only asserted for BIOS
read cycles (MPIIX does not claim the write cycle).
1:0
Reserved.
3.2.11. FDCE—FDC ENABLE REGISTER
Address Offset:
Default Value:
Attribute:
4Fh
21h
Read/Write
This register enables/disables accesses to the Floppy Disk on the Extended I/O Bus. This register also
enable/disables coprocessor Error Function, IRQ12/Mouse Function, the DOE# Disk Output Enable signal
(multiplexed with the SMOUT5 signal), and the RTCALE enable signal (multiplexed with the SMOUT4 signal).
Bit
Description
7
Coprocessor Error function Enable. 1=Enable. The FERR# input, when asserted, triggers
IRQ13 (internal). FERR# is also used to gate the IGNNE# output.
6
IRQ12/M Mouse Function Enable. 1=Mouse function. 0=Standard IRQ12 interrupt function.
5
System Management Output 5/Disk Output Enable. 1=DOE# function on the SMOUT5/DOE#
signal. 0=SMOUT5 function on SMOUT5/DOE# (signal reflects the logic level of the SMOUT5 bit
in the SMOUTC Register).
4
System Management Output 4/RTCALE Enable. 1=RTCALE function on the SMOUT4/RTCALE
signal. 0=SMOUT4 function on SMOUT4/RTCALE (signal reflects the logic level of the SMOUT4
bit in the SMOUTC Register).
3
Motherboard DMA 2 Disable: 1=PAD# function is enabled on the MDAK2#/PAD# pin and the
EXTEVNT# function is enabled on the MDRQ2/EXTEVNT# pin. 0 (default)=MDAK2# function is
enabled on the MDAK2#/PAD# pin and the MDRQ2 function is enabled on the
MDRQ2/EXTEVNT# pin.
2
Reserved.
1
Floppy Secondary Address Enable. When bit 1=1 (Enable), PCI accesses to 0370–0375h and
0377h are forwarded to the Extended I/O Bus. When bit 1=0, MPIIX does not claim these PCI
cycles.
0
Floppy Primary Address Enable. When bit 0=1 (Enable), PCI accesses to 03F0–03F5h and
03F7h are forwarded to the Extended I/O Bus. When bit 0=0, MPIIX does not claim these PCI
cycles.
32
PRELIMINARY