I82371MX Datasheet, PDF (37/133 Pages) Intel Corporation – INTEL 430MX PCISET 82371MX MOBILE PCI I/O IDE XCELERATOR (MPIIX)

E
82371MX (MPIIX)
3.2.17. AUDIOE—AUDIO ENABLE REGISTER
Address Offset:
Default Value:
Attribute:
7Eh
00h
Read/Write
This register enables/disables the audio I/O channel and, when enabled, selects the I/O address.
Bit
Description
7
Audio Enable. 1=Enable (forwards PCI I/O accesses to the address range with the base
address selected by bits [3:2] of this register (2x0−2xFh) to the Extended I/O Bus. 0=Disable.
6:4
Reserved.
3:2
Audio I/O Address. These bits select the I/O address for the audio device, when enabled via bit
7 of this register .
Bits [3:2] I/O Address
00
0220h
01
0230h
10
0240h
11
0250h
1:0
Reserved.
3.2.18. DMADS—DMA CH[7:5] DATA SIZE REGISTER
Address Offset:
Default Value:
Attribute:
7Fh
E0h
Read/Write
This register selects between 8-bit and 16-bit DMA device data size for DMA channels [7:5].
Bit
Description
7
Channel 7 16/8-Bit I/O Count By Words (CH7DS). 1=16-bit, count by word. 0=8-bit, count by
byte.
6
Channel 6 16/8-Bit I/O Count By Words (CH6DS). 1=16-bit, count by word. 0=8-bit, count by
byte.
5
Channel 5 16/8-Bit I/O Count By Words (CH5DS). 1=16-bit, count by word. 0=8-bit, count by
byte.
4:0
Reserved. Read as 0.
PRELIMINARY
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