I82371MX Datasheet, PDF (101/133 Pages) Intel Corporation – INTEL 430MX PCISET 82371MX MOBILE PCI I/O IDE XCELERATOR (MPIIX)

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82371MX (MPIIX)
4.7. Interrupts
The MPIIX provides an ISA compatible interrupt controller which incorporates the functionality of two 82C59
interrupt controllers. The two controllers are cascaded so that 13 external and three internal interrupts are
possible. The master interrupt controller provides IRQ [7:0] and the slave interrupt controller provides IRQ [15:8]
(Figure 10). The three internal interrupts are used for internal functions only and are not available to the user.
IRQ2 is used to cascade the two controllers together. IRQ0 is used as a system timer interrupt and is tied to
Interval Timer 1, Counter 0. IRQ13 is connected internally to FERR#. The remaining 13 interrupt lines
(IRQ[15,12:9,8#,7:3,1] are available for external system interrupts. Edge or level sense selection is
programmable on an individual channel-by-channel basis.
The Interrupt unit also supports interrupt steering. The MPIIX can be programmed to allow the two PCI active
low interrupts (PIRQ[A,B]#) to be internally routed to one of 11 interrupts (IRQ[15,14,12:9,7:3]. In addition, an
interrupt signal is dedicated to motherboard devices (MIRQ#) may be routed to any of the 11 interrupts.
The Interrupt Controller consists of two separate 82C59 cores. Interrupt Controller 1 (CNTRL-1) and Interrupt
Controller 2 (CNTRL-2) are initialized separately and can be programmed to operate in different modes. The
default settings are: 80x86 Mode, Edge Sensitive (IRQ[15:0]) Detection, Normal EOI, Non-Buffered Mode,
Special Fully Nested Mode disabled, and Cascade Mode. CNTRL-1 is connected as the Master Interrupt
Controller and CNTRL-2 is connected as the Slave Interrupt Controller.
Note that IRQ13 is generated internally (as part of the coprocessor error support) by the MPIIX. IRQ12/M is
generated internally (as part of the mouse support) when bit 6 in the FDCE is set to a 1. When set to a 0, the
standard IRQ12 function is provided and IRQ12 appears externally.
IRQ8#
IRQ9
IRQ10
IRQ11
IRQ12/Mouse
FERR#
IRQ14
IRQ15
0#
1
2
82C59
Core
3
4 ^{Controller 2}
5
6 (Slave)
7
Timer 1
Counter 0
INTR
IRQ1
IRQ3
IRQ4
IRQ5
IRQ6
IRQ7
0
1
2
82C59
Core
3
4 ^{Controller 1}
5
6 (Master)
7
INTR
(To CPU)
Figure 10. Block Diagram Of The Interrupt Controller
052510
4.7.1. PROGRAMMING THE INTERRUPT CONTROLLER
The Interrupt Controller accepts two types of command words generated by the CPU or bus master:
1. Initialization Command Words (ICWs): Before normal operation can begin, each Interrupt Controller in the
system must be initialized. In the 82C59, this is a two- to four-byte sequence. However, for the MPIIX, each
controller must be initialized with a four-byte sequence. This four-byte sequence is required to configure the
interrupt controller correctly for the MPIIX implementation. This implementation is ISA-compatible. The four
initialization command words are referred to by their acronyms: ICW1, ICW2, ICW3, and ICW4. The base
address for each interrupt controller is a fixed location in the I/O memory space, at 0020h for CNTRL-1 and at
00A0h for CNTRL-2.
PRELIMINARY
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