I82371MX Datasheet, PDF (4/133 Pages) Intel Corporation – INTEL 430MX PCISET 82371MX MOBILE PCI I/O IDE XCELERATOR (MPIIX)

82371MX (MPIIX)
E
3.2.25. PAC[5:1]—PROGRAMMABLE ADDRESS CONTROL REGISTER .........................................41
3.2.26. PAMA—PROGRAMMABLE ADDRESS MASK A REGISTER ..................................................41
3.2.27. PAMB—PROGRAMMABLE ADDRESS MASK B REGISTER ..................................................42
3.2.28. IOCA—I/O CONFIGURATION ADDRESS REGISTER .............................................................42
3.2.29. PAMC—PROGRAMMABLE ADDRESS MASK C REGISTER .................................................43
3.2.30. PADE[2:0]—PERIPHERAL ACCESS DETECT ENABLE REGISTERS ..................................43
3.2.31. LTADEV3—Local Trap Address for Device 3 Register .............................................................44
3.2.32. LTMDEV3—Local Trap Mask for Device 3 Register ...................................................................44
3.2.33. LTSMIE—Local Trap SMI Enable Register ................................................................................44
3.2.34. LTSMIS—Local Trap SMI Status Register ..................................................................................45
3.2.35. LSBSMIE—Local Standby SMI Enable Register ........................................................................45
3.2.36. LSBTRE—Local Standby Timer Reload Enable Register ..........................................................46
3.2.37. LSBSMIS—Local Standby SMI Status Register ..........................................................................47
3.2.38. LSTBTIDE—Local Standby IDE Timer Register .........................................................................47
3.2.39. LSBTAUD—Local Standby Audio Timer Register ......................................................................48
3.2.40. LSBTCOM—Local Standby COM Timer Register .......................................................................48
3.2.41. LSBTDEV1—Local Standby Device 1 Timer Register ...............................................................48
3.2.42. LSBTDEV2—Local Standby Device 2 Timer Register ...............................................................49
3.2.43. LSBTDEV3—Local Standby Device 3 Timer Register ...............................................................49
3.2.44. SESMIT—Software/EXTSMI# SMI Delay Timer Register ..........................................................49
3.2.45. SUSSMIT—Suspend SMI Delay Timer Register ........................................................................50
3.2.46. GSBTMR—Global Standby Timer Register .................................................................................50
3.2.47. CLKTHSBYT — Clock Throttle Standby Timer Register ............................................................50
3.2.48. SYSMGNTC—System Management Control Register ...............................................................51
3.2.49. SYSSMIE—System SMI Enable Register ...................................................................................51
3.2.50. MISCSMIE—Misc SMI Enable Register ......................................................................................52
3.2.51. GSMIE—Global SMI Enable Register ..........................................................................................52
3.2.52. SYSSMIS—System SMI STATUS Register ................................................................................53
3.2.53. MISCSMIS—Miscellaneous SMI STATUS Register ...................................................................53
3.2.54. GSMIS — Global SMI STATUS Register ....................................................................................54
3.2.55. SUSRSMC1—Suspend/Resume Control 1 Register ..................................................................54
3.2.56. SUSRSMC2—Suspend/Resume Control 2 Register ..................................................................55
3.2.57. SMOUTC—SMOUT Control Register ..........................................................................................55
3.2.58. SYSEVNTE0—System EVENT Enable 0 Register ....................................................................56
3.2.59. SYSEVNTE1—System EVENT Enable 1 Register ....................................................................56
3.2.60. SYSEVNTE2—System EVENT Enable 2 Register ....................................................................57
3.2.61. BSTCLKT — Burst Count Timer Register ....................................................................................57
3.2.62. CLKC—Clock Control Register ....................................................................................................58
3.2.63. STPCLKLT—STPCLK# Low Timer Register ..............................................................................58
3.2.64. STPCLKHT—STPCLK# High Timer Count .................................................................................59
3.2.65. STPBRKE0—Stop Break Event Enable 0 Register ....................................................................59
3.2.66. STPBRKE1—Stop Break Event Enable 1 Register ....................................................................60
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PRELIMINARY